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Document HS400 DQS trim value device tree property. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
113 lines
4.4 KiB
Plaintext
113 lines
4.4 KiB
Plaintext
* NVIDIA Tegra Secure Digital Host Controller
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This controller on Tegra family SoCs provides an interface for MMC, SD,
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and SDIO types of memory cards.
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This file documents differences between the core properties described
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by mmc.txt and the properties used by the sdhci-tegra driver.
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Required properties:
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- compatible : should be one of:
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- "nvidia,tegra20-sdhci": for Tegra20
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- "nvidia,tegra30-sdhci": for Tegra30
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- "nvidia,tegra114-sdhci": for Tegra114
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- "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
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- "nvidia,tegra210-sdhci": for Tegra210
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- "nvidia,tegra186-sdhci": for Tegra186
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- sdhci
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Optional properties:
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- power-gpios : Specify GPIOs for power control
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Example:
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = <47>;
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clocks = <&tegra_car 14>;
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resets = <&tegra_car 14>;
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reset-names = "sdhci";
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cd-gpios = <&gpio 69 0>; /* gpio PI5 */
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wp-gpios = <&gpio 57 0>; /* gpio PH1 */
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power-gpios = <&gpio 155 0>; /* gpio PT3 */
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bus-width = <8>;
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};
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Optional properties for Tegra210 and Tegra186:
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- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
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configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
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for controllers supporting multiple voltage levels. The order of names
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should correspond to the pin configuration states in pinctrl-0 and
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pinctrl-1.
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- nvidia,only-1-8-v : The presence of this property indicates that the
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controller operates at a 1.8 V fixed I/O voltage.
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- nvidia,pad-autocal-pull-up-offset-3v3,
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nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
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calibration offsets for 3.3 V signaling modes.
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- nvidia,pad-autocal-pull-up-offset-1v8,
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nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
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calibration offsets for 1.8 V signaling modes.
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- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
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nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
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strength used as a fallback in case the automatic calibration times
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out on a 3.3 V signaling mode.
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- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
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nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
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strength used as a fallback in case the automatic calibration times
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out on a 1.8 V signaling mode.
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- nvidia,pad-autocal-pull-up-offset-sdr104,
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nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
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calibration offsets for SDR104 mode.
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- nvidia,pad-autocal-pull-up-offset-hs400,
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nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
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calibration offsets for HS400 mode.
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- nvidia,default-tap : Specify the default inbound sampling clock
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trimmer value for non-tunable modes.
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- nvidia,default-trim : Specify the default outbound clock trimmer
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value.
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- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
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Notes on the pad calibration pull up and pulldown offset values:
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- The property values are drive codes which are programmed into the
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PD_OFFSET and PU_OFFSET sections of the
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SDHCI_TEGRA_AUTO_CAL_CONFIG register.
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- A higher value corresponds to higher drive strength. Please refer
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to the reference manual of the SoC for correct values.
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- The SDR104 and HS400 timing specific values are used in
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corresponding modes if specified.
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Notes on tap and trim values:
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- The values are used for compensating trace length differences
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by adjusting the sampling point.
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- The values are programmed to the Vendor Clock Control Register.
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Please refer to the reference manual of the SoC for correct
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values.
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- The DQS trim values are only used on controllers which support
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HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
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HS400.
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Example:
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sdhci@700b0000 {
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compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
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reg = <0x0 0x700b0000 0x0 0x200>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
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clock-names = "sdhci";
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resets = <&tegra_car 14>;
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reset-names = "sdhci";
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
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status = "disabled";
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};
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