mirror of
https://github.com/torvalds/linux.git
synced 2024-11-27 14:41:39 +00:00
7fd123e544
Update the 64s GENERIC_CPU option. POWER4 support has been dropped, so make that clear in the option name. The POWER5_CPU option is dropped because it's uncommon, and GENERIC_CPU covers it. -mtune= before power8 is dropped because the minimum gcc version supports power8, and tuning is made consistent between big and little endian. A 970 option is added for PowerPC 970 / G5 because they still have a user base, and -mtune=power8 does not generate good code for the 970. This also updates the ISA versions document to add Power4/Power4+ because I didn't realise Power4+ used 2.01. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220921014103.587954-2-npiggin@gmail.com
102 lines
2.8 KiB
ReStructuredText
102 lines
2.8 KiB
ReStructuredText
==========================
|
|
CPU to ISA Version Mapping
|
|
==========================
|
|
|
|
Mapping of some CPU versions to relevant ISA versions.
|
|
|
|
Note Power4 and Power4+ are not supported.
|
|
|
|
========= ====================================================================
|
|
CPU Architecture version
|
|
========= ====================================================================
|
|
Power10 Power ISA v3.1
|
|
Power9 Power ISA v3.0B
|
|
Power8 Power ISA v2.07
|
|
e6500 Power ISA v2.06 with some exceptions
|
|
e5500 Power ISA v2.06 with some exceptions, no Altivec
|
|
Power7 Power ISA v2.06
|
|
Power6 Power ISA v2.05
|
|
PA6T Power ISA v2.04
|
|
Cell PPU - Power ISA v2.02 with some minor exceptions
|
|
- Plus Altivec/VMX ~= 2.03
|
|
Power5++ Power ISA v2.04 (no VMX)
|
|
Power5+ Power ISA v2.03
|
|
Power5 - PowerPC User Instruction Set Architecture Book I v2.02
|
|
- PowerPC Virtual Environment Architecture Book II v2.02
|
|
- PowerPC Operating Environment Architecture Book III v2.02
|
|
PPC970 - PowerPC User Instruction Set Architecture Book I v2.01
|
|
- PowerPC Virtual Environment Architecture Book II v2.01
|
|
- PowerPC Operating Environment Architecture Book III v2.01
|
|
- Plus Altivec/VMX ~= 2.03
|
|
Power4+ - PowerPC User Instruction Set Architecture Book I v2.01
|
|
- PowerPC Virtual Environment Architecture Book II v2.01
|
|
- PowerPC Operating Environment Architecture Book III v2.01
|
|
Power4 - PowerPC User Instruction Set Architecture Book I v2.00
|
|
- PowerPC Virtual Environment Architecture Book II v2.00
|
|
- PowerPC Operating Environment Architecture Book III v2.00
|
|
========= ====================================================================
|
|
|
|
|
|
Key Features
|
|
------------
|
|
|
|
========== ==================
|
|
CPU VMX (aka. Altivec)
|
|
========== ==================
|
|
Power10 Yes
|
|
Power9 Yes
|
|
Power8 Yes
|
|
e6500 Yes
|
|
e5500 No
|
|
Power7 Yes
|
|
Power6 Yes
|
|
PA6T Yes
|
|
Cell PPU Yes
|
|
Power5++ No
|
|
Power5+ No
|
|
Power5 No
|
|
PPC970 Yes
|
|
Power4+ No
|
|
Power4 No
|
|
========== ==================
|
|
|
|
========== ====
|
|
CPU VSX
|
|
========== ====
|
|
Power10 Yes
|
|
Power9 Yes
|
|
Power8 Yes
|
|
e6500 No
|
|
e5500 No
|
|
Power7 Yes
|
|
Power6 No
|
|
PA6T No
|
|
Cell PPU No
|
|
Power5++ No
|
|
Power5+ No
|
|
Power5 No
|
|
PPC970 No
|
|
Power4+ No
|
|
Power4 No
|
|
========== ====
|
|
|
|
========== ====================================
|
|
CPU Transactional Memory
|
|
========== ====================================
|
|
Power10 No (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture")
|
|
Power9 Yes (* see transactional_memory.txt)
|
|
Power8 Yes
|
|
e6500 No
|
|
e5500 No
|
|
Power7 No
|
|
Power6 No
|
|
PA6T No
|
|
Cell PPU No
|
|
Power5++ No
|
|
Power5+ No
|
|
Power5 No
|
|
PPC970 No
|
|
Power4+ No
|
|
Power4 No
|
|
========== ====================================
|