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Describe the DEXCR and document how to configure it. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230616034846.311705-9-bgray@linux.ibm.com
59 lines
2.4 KiB
ReStructuredText
59 lines
2.4 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0-or-later
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==========================================
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DEXCR (Dynamic Execution Control Register)
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==========================================
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Overview
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========
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The DEXCR is a privileged special purpose register (SPR) introduced in
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PowerPC ISA 3.1B (Power10) that allows per-cpu control over several dynamic
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execution behaviours. These behaviours include speculation (e.g., indirect
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branch target prediction) and enabling return-oriented programming (ROP)
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protection instructions.
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The execution control is exposed in hardware as up to 32 bits ('aspects') in
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the DEXCR. Each aspect controls a certain behaviour, and can be set or cleared
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to enable/disable the aspect. There are several variants of the DEXCR for
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different purposes:
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DEXCR
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A privileged SPR that can control aspects for userspace and kernel space
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HDEXCR
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A hypervisor-privileged SPR that can control aspects for the hypervisor and
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enforce aspects for the kernel and userspace.
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UDEXCR
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An optional ultravisor-privileged SPR that can control aspects for the ultravisor.
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Userspace can examine the current DEXCR state using a dedicated SPR that
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provides a non-privileged read-only view of the userspace DEXCR aspects.
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There is also an SPR that provides a read-only view of the hypervisor enforced
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aspects, which ORed with the userspace DEXCR view gives the effective DEXCR
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state for a process.
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Configuration
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=============
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The DEXCR is currently unconfigurable. All threads are run with the
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NPHIE aspect enabled.
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coredump and ptrace
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===================
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The userspace values of the DEXCR and HDEXCR (in this order) are exposed under
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``NT_PPC_DEXCR``. These are each 64 bits and readonly, and are intended to
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assist with core dumps. The DEXCR may be made writable in future. The top 32
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bits of both registers (corresponding to the non-userspace bits) are masked off.
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If the kernel config ``CONFIG_CHECKPOINT_RESTORE`` is enabled, then
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``NT_PPC_HASHKEYR`` is available and exposes the HASHKEYR value of the process
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for reading and writing. This is a tradeoff between increased security and
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checkpoint/restore support: a process should normally have no need to know its
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secret key, but restoring a process requires setting its original key. The key
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therefore appears in core dumps, and an attacker may be able to retrieve it from
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a coredump and effectively bypass ROP protection on any threads that share this
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key (potentially all threads from the same parent that have not run ``exec()``).
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