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a5ebba6b54
These are various power management related changes, mainly concerning
cpuidle on i.MX and OMAP, as well as a the move of the omap smartreflex
driver to live in the power subsystem.
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Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc power management changes from Arnd Bergmann:
"These are various power management related changes, mainly concerning
cpuidle on i.MX and OMAP, as well as a the move of the omap
smartreflex driver to live in the power subsystem."
Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h}
* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
ARM: OMAP2+: do not allow SmartReflex to be built as a module
ARM: OMAP2: Use hwmod to initialize mmc for 2420
ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
ARM: OMAP3: PM: call pre/post transition per powerdomain
ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
ARM: OMAP3+: PRM: Enable IO wake up
ARM: OMAP4: PRM: Add IO Daisychain support
ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3: PM: correct enable/disable of daisy io chain
ARM: OMAP2+: PRM: fix compile for OMAP4-only build
W1: OMAP HDQ1W: use runtime PM
ARM: OMAP2+: HDQ1W: use omap_device
W1: OMAP HDQ1W: use 32-bit register accesses
W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
...
260 lines
9.8 KiB
C
260 lines
9.8 KiB
C
/*
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* OMAP2/3/4 powerdomain control
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*
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* Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
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* Copyright (C) 2007-2011 Nokia Corporation
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*
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX This should be moved to the mach-omap2/ directory at the earliest
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* opportunity.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
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#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
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#include <linux/types.h>
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#include <linux/list.h>
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#include <linux/atomic.h>
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#include <plat/cpu.h>
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#include "voltage.h"
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/* Powerdomain basic power states */
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#define PWRDM_POWER_OFF 0x0
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#define PWRDM_POWER_RET 0x1
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#define PWRDM_POWER_INACTIVE 0x2
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#define PWRDM_POWER_ON 0x3
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#define PWRDM_MAX_PWRSTS 4
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/* Powerdomain allowable state bitfields */
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#define PWRSTS_ON (1 << PWRDM_POWER_ON)
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#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
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#define PWRSTS_RET (1 << PWRDM_POWER_RET)
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#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
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/* Powerdomain flags */
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#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
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#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
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* in MEM bank 1 position. This is
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* true for OMAP3430
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*/
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#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
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* support to transition from a
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* sleep state to a lower sleep
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* state without waking up the
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* powerdomain
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*/
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/*
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* Number of memory banks that are power-controllable. On OMAP4430, the
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* maximum is 5.
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*/
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#define PWRDM_MAX_MEM_BANKS 5
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/*
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* Maximum number of clockdomains that can be associated with a powerdomain.
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* PER powerdomain on AM33XX is the worst case
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*/
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#define PWRDM_MAX_CLKDMS 11
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/* XXX A completely arbitrary number. What is reasonable here? */
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#define PWRDM_TRANSITION_BAILOUT 100000
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struct clockdomain;
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struct powerdomain;
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/**
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* struct powerdomain - OMAP powerdomain
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* @name: Powerdomain name
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* @voltdm: voltagedomain containing this powerdomain
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* @prcm_offs: the address offset from CM_BASE/PRM_BASE
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* @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
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* @pwrsts: Possible powerdomain power states
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* @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
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* @flags: Powerdomain flags
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* @banks: Number of software-controllable memory banks in this powerdomain
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* @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
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* @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
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* @pwrdm_clkdms: Clockdomains in this powerdomain
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* @node: list_head linking all powerdomains
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* @voltdm_node: list_head linking all powerdomains in a voltagedomain
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* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
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* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
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* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
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* in @pwrstctrl_offs
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* @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
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* @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
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* @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
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* @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
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* in @pwrstctrl_offs
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* @state:
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* @state_counter:
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* @timer:
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* @state_timer:
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*
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* @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
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*/
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struct powerdomain {
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const char *name;
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union {
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const char *name;
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struct voltagedomain *ptr;
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} voltdm;
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const s16 prcm_offs;
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const u8 pwrsts;
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const u8 pwrsts_logic_ret;
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const u8 flags;
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const u8 banks;
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const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
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const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
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const u8 prcm_partition;
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struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
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struct list_head node;
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struct list_head voltdm_node;
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int state;
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unsigned state_counter[PWRDM_MAX_PWRSTS];
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unsigned ret_logic_off_counter;
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unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
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const u8 pwrstctrl_offs;
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const u8 pwrstst_offs;
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const u32 logicretstate_mask;
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const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
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const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
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const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
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const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
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#ifdef CONFIG_PM_DEBUG
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s64 timer;
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s64 state_timer[PWRDM_MAX_PWRSTS];
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#endif
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};
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/**
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* struct pwrdm_ops - Arch specific function implementations
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* @pwrdm_set_next_pwrst: Set the target power state for a pd
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* @pwrdm_read_next_pwrst: Read the target power state set for a pd
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* @pwrdm_read_pwrst: Read the current power state of a pd
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* @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
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* @pwrdm_set_logic_retst: Set the logic state in RET for a pd
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* @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
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* @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
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* @pwrdm_read_logic_pwrst: Read the current logic state of a pd
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* @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
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* @pwrdm_read_logic_retst: Read the logic state in RET for a pd
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* @pwrdm_read_mem_pwrst: Read the current memory state of a pd
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* @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
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* @pwrdm_read_mem_retst: Read the memory state in RET for a pd
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* @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
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* @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
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* @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
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* @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
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* @pwrdm_wait_transition: Wait for a pd state transition to complete
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*/
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struct pwrdm_ops {
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int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
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int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
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int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
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int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
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int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
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int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
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int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
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int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
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int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
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};
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int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
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int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
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int pwrdm_complete_init(void);
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struct powerdomain *pwrdm_lookup(const char *name);
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int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
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void *user);
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int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
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void *user);
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int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
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int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
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int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
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int (*fn)(struct powerdomain *pwrdm,
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struct clockdomain *clkdm));
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struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
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int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
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int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
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int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
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int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
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int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
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int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
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int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
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bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
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int pwrdm_wait_transition(struct powerdomain *pwrdm);
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int pwrdm_state_switch(struct powerdomain *pwrdm);
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int pwrdm_pre_transition(struct powerdomain *pwrdm);
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int pwrdm_post_transition(struct powerdomain *pwrdm);
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int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
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int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
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bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
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extern void omap242x_powerdomains_init(void);
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extern void omap243x_powerdomains_init(void);
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extern void omap3xxx_powerdomains_init(void);
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extern void am33xx_powerdomains_init(void);
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extern void omap44xx_powerdomains_init(void);
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extern struct pwrdm_ops omap2_pwrdm_operations;
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extern struct pwrdm_ops omap3_pwrdm_operations;
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extern struct pwrdm_ops am33xx_pwrdm_operations;
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extern struct pwrdm_ops omap4_pwrdm_operations;
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/* Common Internal functions used across OMAP rev's */
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extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
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extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
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extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
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extern struct powerdomain wkup_omap2_pwrdm;
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extern struct powerdomain gfx_omap2_pwrdm;
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#endif
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