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6e11940ab3
- Make clk_ops::determine_rate mandatory for muxes * clk-renesas: clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() clk: renesas: mstp: Convert to readl_poll_timeout_atomic() clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic() iopoll: Do not use timekeeping in read_poll_timeout_atomic() iopoll: Call cpu_relax() in busy loops clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write clk: renesas: r8a779a0: Add PWM clock * clk-determine-rate: (71 commits) clk: sprd: composite: Simplify determine_rate implementation ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate() clk: Fix best_parent_rate after moving code into a separate function clk: Forbid to register a mux without determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate clk: tegra: super: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5341: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate ... * clk-allwinner: clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux * clk-samsung: clk: samsung: add CONFIG_OF dependency clk: samsung: Re-add support for Exynos4212 CPU clock clk: samsung: Add Exynos4212 compatible to CLKOUT driver dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible * clk-amlogic: MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK clk: meson: pll: remove unneeded semicolon clk: meson: a1: Staticize rtc clk clk: meson: a1: add Amlogic A1 Peripherals clock controller driver clk: meson: a1: add Amlogic A1 PLL clock controller driver clk: meson: introduce new pll power-on sequence for A1 SoC family clk: meson: make pll rst bit as optional dt-bindings: clock: meson: add A1 Peripherals clock controller bindings dt-bindings: clock: meson: add A1 PLL clock controller bindings |
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|---|---|---|
| .. | ||
| clk-div6.c | ||
| clk-div6.h | ||
| clk-emev2.c | ||
| clk-mstp.c | ||
| clk-r8a73a4.c | ||
| clk-r8a7740.c | ||
| clk-r8a7778.c | ||
| clk-r8a7779.c | ||
| clk-rz.c | ||
| clk-sh73a0.c | ||
| Kconfig | ||
| Makefile | ||
| r7s9210-cpg-mssr.c | ||
| r8a774a1-cpg-mssr.c | ||
| r8a774b1-cpg-mssr.c | ||
| r8a774c0-cpg-mssr.c | ||
| r8a774e1-cpg-mssr.c | ||
| r8a779a0-cpg-mssr.c | ||
| r8a779f0-cpg-mssr.c | ||
| r8a779g0-cpg-mssr.c | ||
| r8a7742-cpg-mssr.c | ||
| r8a7743-cpg-mssr.c | ||
| r8a7745-cpg-mssr.c | ||
| r8a7790-cpg-mssr.c | ||
| r8a7791-cpg-mssr.c | ||
| r8a7792-cpg-mssr.c | ||
| r8a7794-cpg-mssr.c | ||
| r8a7795-cpg-mssr.c | ||
| r8a7796-cpg-mssr.c | ||
| r8a77470-cpg-mssr.c | ||
| r8a77965-cpg-mssr.c | ||
| r8a77970-cpg-mssr.c | ||
| r8a77980-cpg-mssr.c | ||
| r8a77990-cpg-mssr.c | ||
| r8a77995-cpg-mssr.c | ||
| r9a06g032-clocks.c | ||
| r9a07g043-cpg.c | ||
| r9a07g044-cpg.c | ||
| r9a09g011-cpg.c | ||
| rcar-cpg-lib.c | ||
| rcar-cpg-lib.h | ||
| rcar-gen2-cpg.c | ||
| rcar-gen2-cpg.h | ||
| rcar-gen3-cpg.c | ||
| rcar-gen3-cpg.h | ||
| rcar-gen4-cpg.c | ||
| rcar-gen4-cpg.h | ||
| rcar-usb2-clock-sel.c | ||
| renesas-cpg-mssr.c | ||
| renesas-cpg-mssr.h | ||
| rzg2l-cpg.c | ||
| rzg2l-cpg.h | ||