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ac1edcc579
Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. N.B. Leon apparently never uses initial BAR values, so it didn't matter that we never fixed up the I/O resources from bus address to CPU addresses. Other sparc uses pci_of_scan_bus(), which sets device resources directly to CPU addresses, not bus addresses, so it didn't need pcibios_fixup_bus() either. But by telling the core about the offsets, we can nuke pcibios_resource_to_bus(). CC: "David S. Miller" <davem@davemloft.net> CC: sparclinux@vger.kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
213 lines
5.2 KiB
C
213 lines
5.2 KiB
C
/*
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* leon_pci.c: LEON Host PCI support
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*
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* Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
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*
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* Code is partially derived from pcic.c
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*/
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#include <linux/of_device.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/export.h>
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#include <asm/leon.h>
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#include <asm/leon_pci.h>
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/* The LEON architecture does not rely on a BIOS or bootloader to setup
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* PCI for us. The Linux generic routines are used to setup resources,
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* reset values of configuration-space register settings are preserved.
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*
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* PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
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* accessed through a Window which is translated to low 64KB in PCI space, the
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* first 4KB is not used so 60KB is available.
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*/
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void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
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{
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LIST_HEAD(resources);
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struct pci_bus *root_bus;
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pci_add_resource_offset(&resources, &info->io_space,
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info->io_space.start - 0x1000);
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pci_add_resource(&resources, &info->mem_space);
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root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
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&resources);
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if (root_bus) {
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/* Setup IRQs of all devices using custom routines */
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pci_fixup_irqs(pci_common_swizzle, info->map_irq);
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/* Assign devices with resources */
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pci_assign_unassigned_resources();
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} else {
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pci_free_resource_list(&resources);
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}
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}
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void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
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{
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struct leon_pci_info *info = pbus->sysdata;
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struct pci_dev *dev;
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int i, has_io, has_mem;
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u16 cmd;
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list_for_each_entry(dev, &pbus->devices, bus_list) {
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/*
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* We can not rely on that the bootloader has enabled I/O
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* or memory access to PCI devices. Instead we enable it here
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* if the device has BARs of respective type.
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*/
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has_io = has_mem = 0;
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for (i = 0; i < PCI_ROM_RESOURCE; i++) {
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unsigned long f = dev->resource[i].flags;
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if (f & IORESOURCE_IO)
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has_io = 1;
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else if (f & IORESOURCE_MEM)
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has_mem = 1;
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}
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/* ROM BARs are mapped into 32-bit memory space */
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if (dev->resource[PCI_ROM_RESOURCE].end != 0) {
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dev->resource[PCI_ROM_RESOURCE].flags |=
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IORESOURCE_ROM_ENABLE;
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has_mem = 1;
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}
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pci_bus_read_config_word(pbus, dev->devfn, PCI_COMMAND, &cmd);
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if (has_io && !(cmd & PCI_COMMAND_IO)) {
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#ifdef CONFIG_PCI_DEBUG
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printk(KERN_INFO "LEONPCI: Enabling I/O for dev %s\n",
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pci_name(dev));
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#endif
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cmd |= PCI_COMMAND_IO;
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pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
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cmd);
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}
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if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
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#ifdef CONFIG_PCI_DEBUG
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printk(KERN_INFO "LEONPCI: Enabling MEMORY for dev"
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"%s\n", pci_name(dev));
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#endif
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cmd |= PCI_COMMAND_MEMORY;
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pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND,
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cmd);
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}
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}
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}
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/*
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* Other archs parse arguments here.
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*/
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char * __devinit pcibios_setup(char *str)
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{
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return str;
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}
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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return pci_enable_resources(dev, mask);
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}
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struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
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{
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/*
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* Currently the OpenBoot nodes are not connected with the PCI device,
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* this is because the LEON PROM does not create PCI nodes. Eventually
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* this will change and the same approach as pcic.c can be used to
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* match PROM nodes with pci devices.
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*/
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return NULL;
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}
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EXPORT_SYMBOL(pci_device_to_OF_node);
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void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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#ifdef CONFIG_PCI_DEBUG
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printk(KERN_DEBUG "LEONPCI: Assigning IRQ %02d to %s\n", irq,
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pci_name(dev));
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#endif
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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/* in/out routines taken from pcic.c
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*
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* This probably belongs here rather than ioport.c because
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* we do not want this crud linked into SBus kernels.
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* Also, think for a moment about likes of floppy.c that
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* include architecture specific parts. They may want to redefine ins/outs.
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*
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* We do not use horrible macros here because we want to
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* advance pointer by sizeof(size).
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*/
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void outsb(unsigned long addr, const void *src, unsigned long count)
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{
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while (count) {
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count -= 1;
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outb(*(const char *)src, addr);
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src += 1;
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/* addr += 1; */
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}
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}
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EXPORT_SYMBOL(outsb);
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void outsw(unsigned long addr, const void *src, unsigned long count)
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{
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while (count) {
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count -= 2;
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outw(*(const short *)src, addr);
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src += 2;
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/* addr += 2; */
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}
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}
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EXPORT_SYMBOL(outsw);
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void outsl(unsigned long addr, const void *src, unsigned long count)
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{
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while (count) {
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count -= 4;
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outl(*(const long *)src, addr);
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src += 4;
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/* addr += 4; */
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}
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}
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EXPORT_SYMBOL(outsl);
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void insb(unsigned long addr, void *dst, unsigned long count)
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{
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while (count) {
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count -= 1;
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*(unsigned char *)dst = inb(addr);
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dst += 1;
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/* addr += 1; */
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}
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}
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EXPORT_SYMBOL(insb);
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void insw(unsigned long addr, void *dst, unsigned long count)
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{
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while (count) {
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count -= 2;
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*(unsigned short *)dst = inw(addr);
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dst += 2;
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/* addr += 2; */
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}
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}
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EXPORT_SYMBOL(insw);
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void insl(unsigned long addr, void *dst, unsigned long count)
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{
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while (count) {
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count -= 4;
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/*
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* XXX I am sure we are in for an unaligned trap here.
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*/
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*(unsigned long *)dst = inl(addr);
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dst += 4;
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/* addr += 4; */
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}
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}
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EXPORT_SYMBOL(insl);
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