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47c42e6b41
The cr4_pae flag is a bit of a misnomer, its purpose is really to track
whether the guest PTE that is being shadowed is a 4-byte entry or an
8-byte entry. Prior to supporting nested EPT, the size of the gpte was
reflected purely by CR4.PAE. KVM fudged things a bit for direct sptes,
but it was mostly harmless since the size of the gpte never mattered.
Now that a spte may be tracking an indirect EPT entry, relying on
CR4.PAE is wrong and ill-named.
For direct shadow pages, force the gpte_size to '1' as they are always
8-byte entries; EPT entries can only be 8-bytes and KVM always uses
8-byte entries for NPT and its identity map (when running with EPT but
not unrestricted guest).
Likewise, nested EPT entries are always 8-bytes. Nested EPT presents a
unique scenario as the size of the entries are not dictated by CR4.PAE,
but neither is the shadow page a direct map. To handle this scenario,
set cr0_wp=1 and smap_andnot_wp=1, an otherwise impossible combination,
to denote a nested EPT shadow page. Use the information to avoid
incorrectly zapping an unsync'd indirect page in __kvm_sync_page().
Providing a consistent and accurate gpte_size fixes a bug reported by
Vitaly where fast_cr3_switch() always fails when switching from L2 to
L1 as kvm_mmu_get_page() would force role.cr4_pae=0 for direct pages,
whereas kvm_calc_mmu_role_common() would set it according to CR4.PAE.
Fixes:
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.. | ||
vmx | ||
cpuid.c | ||
cpuid.h | ||
debugfs.c | ||
emulate.c | ||
hyperv.c | ||
hyperv.h | ||
i8254.c | ||
i8254.h | ||
i8259.c | ||
ioapic.c | ||
ioapic.h | ||
irq_comm.c | ||
irq.c | ||
irq.h | ||
Kconfig | ||
kvm_cache_regs.h | ||
lapic.c | ||
lapic.h | ||
Makefile | ||
mmu_audit.c | ||
mmu.c | ||
mmu.h | ||
mmutrace.h | ||
mtrr.c | ||
page_track.c | ||
paging_tmpl.h | ||
pmu_amd.c | ||
pmu.c | ||
pmu.h | ||
svm.c | ||
trace.h | ||
tss.h | ||
x86.c | ||
x86.h |