Heiko Stuebner 4791eb61db clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac ... The dwmac ethernet controller on the rk3288 supports phys connected via rgmii and rmii. With rgmii phys it is expected that the mac clock is provided externally while with rmii phys the clock can be external but also generated from the plls. In the later case it of course needs be at 50MHz, which gets set from the dwmac_rk driver. As most devices use a rgmii phy it never surfaced so far that the mac clk mux, doesn't go up one lever to the pll clock in the rmii case with internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag, and thus will not set the correct frequency in most cases. Fixes: b9e4ba5416 ("clk: rockchip: add clock controller for rk3288") Cc: stable@vger.kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-07-06 15:03:23 -07:00
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clk-cpu.c	clk: make several parent names const	2015-06-04 14:27:06 -07:00
clk-mmc-phase.c	clk: make several parent names const	2015-06-04 14:27:06 -07:00
clk-pll.c	clk: make several parent names const	2015-06-04 14:27:06 -07:00
clk-rk3188.c	clk: rockchip: Staticize file-scope declarations	2015-05-05 22:50:42 -07:00
clk-rk3288.c	clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac	2015-07-06 15:03:23 -07:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk: make several parent names const	2015-06-04 14:27:06 -07:00
clk.h	clk: make several parent names const	2015-06-04 14:27:06 -07:00
Makefile	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00