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b4523c87c0
Add support for reading a lower and upper 32bits of a register as a single 64bit register. Also add simplified macros for direct register accesses. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
147 lines
4.2 KiB
C
147 lines
4.2 KiB
C
/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CORESIGHT_PRIV_H
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#define _CORESIGHT_PRIV_H
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/coresight.h>
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#include <linux/pm_runtime.h>
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/*
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* Coresight management registers (0xf00-0xfcc)
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* 0xfa0 - 0xfa4: Management registers in PFTv1.0
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* Trace registers in PFTv1.1
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*/
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#define CORESIGHT_ITCTRL 0xf00
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#define CORESIGHT_CLAIMSET 0xfa0
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#define CORESIGHT_CLAIMCLR 0xfa4
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#define CORESIGHT_LAR 0xfb0
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#define CORESIGHT_LSR 0xfb4
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#define CORESIGHT_AUTHSTATUS 0xfb8
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#define CORESIGHT_DEVID 0xfc8
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#define CORESIGHT_DEVTYPE 0xfcc
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#define TIMEOUT_US 100
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#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
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#define ETM_MODE_EXCL_KERN BIT(30)
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#define ETM_MODE_EXCL_USER BIT(31)
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typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
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#define __coresight_simple_func(type, func, name, lo_off, hi_off) \
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static ssize_t name##_show(struct device *_dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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type *drvdata = dev_get_drvdata(_dev->parent); \
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coresight_read_fn fn = func; \
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u64 val; \
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pm_runtime_get_sync(_dev->parent); \
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if (fn) \
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val = (u64)fn(_dev->parent, lo_off); \
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else \
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val = coresight_read_reg_pair(drvdata->base, \
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lo_off, hi_off); \
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pm_runtime_put_sync(_dev->parent); \
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return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \
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} \
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static DEVICE_ATTR_RO(name)
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#define coresight_simple_func(type, func, name, offset) \
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__coresight_simple_func(type, func, name, offset, -1)
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#define coresight_simple_reg32(type, name, offset) \
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__coresight_simple_func(type, NULL, name, offset, -1)
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#define coresight_simple_reg64(type, name, lo_off, hi_off) \
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__coresight_simple_func(type, NULL, name, lo_off, hi_off)
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extern const u32 barrier_pkt[5];
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enum etm_addr_type {
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ETM_ADDR_TYPE_NONE,
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ETM_ADDR_TYPE_SINGLE,
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ETM_ADDR_TYPE_RANGE,
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ETM_ADDR_TYPE_START,
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ETM_ADDR_TYPE_STOP,
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};
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enum cs_mode {
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CS_MODE_DISABLED,
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CS_MODE_SYSFS,
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CS_MODE_PERF,
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};
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/**
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* struct cs_buffer - keep track of a recording session' specifics
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* @cur: index of the current buffer
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* @nr_pages: max number of pages granted to us
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* @offset: offset within the current buffer
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* @data_size: how much we collected in this run
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* @snapshot: is this run in snapshot mode
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* @data_pages: a handle the ring buffer
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*/
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struct cs_buffers {
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unsigned int cur;
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unsigned int nr_pages;
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unsigned long offset;
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local_t data_size;
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bool snapshot;
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void **data_pages;
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};
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static inline void CS_LOCK(void __iomem *addr)
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{
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do {
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/* Wait for things to settle */
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mb();
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writel_relaxed(0x0, addr + CORESIGHT_LAR);
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} while (0);
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}
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static inline void CS_UNLOCK(void __iomem *addr)
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{
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do {
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writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
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/* Make sure everyone has seen this */
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mb();
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} while (0);
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}
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static inline u64
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coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
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{
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u64 val;
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val = readl_relaxed(addr + lo_offset);
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val |= (hi_offset < 0) ? 0 :
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(u64)readl_relaxed(addr + hi_offset) << 32;
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return val;
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}
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void coresight_disable_path(struct list_head *path);
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int coresight_enable_path(struct list_head *path, u32 mode);
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struct coresight_device *coresight_get_sink(struct list_head *path);
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struct coresight_device *coresight_get_enabled_sink(bool reset);
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struct list_head *coresight_build_path(struct coresight_device *csdev,
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struct coresight_device *sink);
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void coresight_release_path(struct list_head *path);
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#ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
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extern int etm_readl_cp14(u32 off, unsigned int *val);
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extern int etm_writel_cp14(u32 off, u32 val);
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#else
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static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
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static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
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#endif
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#endif
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