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471d7ff8b5
POWER4 has been broken since at least the change 49d09bf2a6
("powerpc/64s: Optimise MSR handling in exception handling"), which
requires mtmsrd L=1 support. This was introduced in ISA v2.01, and
POWER4 supports ISA v2.00.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
22 lines
720 B
Makefile
22 lines
720 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
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obj-$(CONFIG_PERF_EVENTS) += callchain.o perf_regs.o
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obj-$(CONFIG_PPC_PERF_CTRS) += core-book3s.o bhrb.o
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obj64-$(CONFIG_PPC_PERF_CTRS) += ppc970-pmu.o power5-pmu.o \
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power5+-pmu.o power6-pmu.o power7-pmu.o \
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isa207-common.o power8-pmu.o power9-pmu.o
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obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
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obj-$(CONFIG_PPC_POWERNV) += imc-pmu.o
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obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
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obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
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obj-$(CONFIG_HV_PERF_CTRS) += hv-24x7.o hv-gpci.o hv-common.o
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obj-$(CONFIG_PPC_8xx) += 8xx-pmu.o
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obj-$(CONFIG_PPC64) += $(obj64-y)
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obj-$(CONFIG_PPC32) += $(obj32-y)
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