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b50e56d81e
In pata_legacy and pata_winbond we've got bugs - cpu_to_le16() instead of cpu_to_le32(). Fortunately, both affected suckers are VLB, thus l-e-only, so we might get away with that unless we hit it with slop == 3 (hadn't checked if playing with badly aligned sg could trigger that). Still buggy... Moreover, pata_legacy, pata_winbond and pata_qdi forgot to initialize pad on the write side of 32bit case in their ->data_xfer(). Hopefully the hardware does't care, but still, sending uninitialized data to it... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jeff Garzik <jeff@garzik.org>
416 lines
9.7 KiB
C
416 lines
9.7 KiB
C
/*
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* pata_qdi.c - QDI VLB ATA controllers
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* (C) 2006 Red Hat <alan@redhat.com>
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*
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* This driver mostly exists as a proof of concept for non PCI devices under
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* libata. While the QDI6580 was 'neat' in 1993 it is no longer terribly
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* useful.
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*
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* Tuning code written from the documentation at
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* http://www.ryston.cz/petr/vlb/qd6500.html
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* http://www.ryston.cz/petr/vlb/qd6580.html
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*
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* Probe code based on drivers/ide/legacy/qd65xx.c
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* Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
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* Samuel Thibault <samuel.thibault@fnac.net>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/platform_device.h>
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#define DRV_NAME "pata_qdi"
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#define DRV_VERSION "0.3.1"
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#define NR_HOST 4 /* Two 6580s */
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struct qdi_data {
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unsigned long timing;
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u8 clock[2];
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u8 last;
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int fast;
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struct platform_device *platform_dev;
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};
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static struct ata_host *qdi_host[NR_HOST];
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static struct qdi_data qdi_data[NR_HOST];
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static int nr_qdi_host;
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#ifdef MODULE
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static int probe_qdi = 1;
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#else
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static int probe_qdi;
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#endif
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static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct ata_timing t;
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struct qdi_data *qdi = ap->host->private_data;
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int active, recovery;
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u8 timing;
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/* Get the timing data in cycles */
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ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
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if (qdi->fast) {
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active = 8 - FIT(t.active, 1, 8);
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recovery = 18 - FIT(t.recover, 3, 18);
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} else {
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active = 9 - FIT(t.active, 2, 9);
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recovery = 15 - FIT(t.recover, 0, 15);
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}
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timing = (recovery << 4) | active | 0x08;
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qdi->clock[adev->devno] = timing;
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outb(timing, qdi->timing);
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}
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static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct ata_timing t;
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struct qdi_data *qdi = ap->host->private_data;
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int active, recovery;
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u8 timing;
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/* Get the timing data in cycles */
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ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
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if (qdi->fast) {
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active = 8 - FIT(t.active, 1, 8);
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recovery = 18 - FIT(t.recover, 3, 18);
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} else {
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active = 9 - FIT(t.active, 2, 9);
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recovery = 15 - FIT(t.recover, 0, 15);
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}
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timing = (recovery << 4) | active | 0x08;
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qdi->clock[adev->devno] = timing;
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outb(timing, qdi->timing);
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/* Clear the FIFO */
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if (adev->class != ATA_DEV_ATA)
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outb(0x5F, (qdi->timing & 0xFFF0) + 3);
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}
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/**
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* qdi_qc_issue_prot - command issue
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* @qc: command pending
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*
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* Called when the libata layer is about to issue a command. We wrap
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* this interface so that we can load the correct ATA timings.
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*/
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static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct qdi_data *qdi = ap->host->private_data;
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if (qdi->clock[adev->devno] != qdi->last) {
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if (adev->pio_mode) {
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qdi->last = qdi->clock[adev->devno];
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outb(qdi->clock[adev->devno], qdi->timing);
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}
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}
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return ata_qc_issue_prot(qc);
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}
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static void qdi_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
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{
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struct ata_port *ap = adev->link->ap;
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int slop = buflen & 3;
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if (ata_id_has_dword_io(adev->id)) {
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if (write_data)
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iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
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else
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ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
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if (unlikely(slop)) {
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__le32 pad = 0;
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if (write_data) {
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memcpy(&pad, buf + buflen - slop, slop);
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iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
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} else {
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pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
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memcpy(buf + buflen - slop, &pad, slop);
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}
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}
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} else
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ata_data_xfer(adev, buf, buflen, write_data);
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}
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static struct scsi_host_template qdi_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations qdi6500_port_ops = {
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.set_piomode = qdi6500_set_piomode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.qc_prep = ata_qc_prep,
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.qc_issue = qdi_qc_issue_prot,
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.data_xfer = qdi_data_xfer,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.port_start = ata_sff_port_start,
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};
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static struct ata_port_operations qdi6580_port_ops = {
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.set_piomode = qdi6580_set_piomode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.qc_prep = ata_qc_prep,
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.qc_issue = qdi_qc_issue_prot,
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.data_xfer = qdi_data_xfer,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.port_start = ata_sff_port_start,
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};
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/**
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* qdi_init_one - attach a qdi interface
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* @type: Type to display
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* @io: I/O port start
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* @irq: interrupt line
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* @fast: True if on a > 33Mhz VLB
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*
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* Register an ISA bus IDE interface. Such interfaces are PIO and we
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* assume do not support IRQ sharing.
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*/
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static __init int qdi_init_one(unsigned long port, int type, unsigned long io, int irq, int fast)
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{
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unsigned long ctl = io + 0x206;
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struct platform_device *pdev;
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struct ata_host *host;
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struct ata_port *ap;
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void __iomem *io_addr, *ctl_addr;
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int ret;
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/*
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* Fill in a probe structure first of all
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*/
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pdev = platform_device_register_simple(DRV_NAME, nr_qdi_host, NULL, 0);
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if (IS_ERR(pdev))
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return PTR_ERR(pdev);
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ret = -ENOMEM;
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io_addr = devm_ioport_map(&pdev->dev, io, 8);
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ctl_addr = devm_ioport_map(&pdev->dev, ctl, 1);
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if (!io_addr || !ctl_addr)
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goto fail;
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ret = -ENOMEM;
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host = ata_host_alloc(&pdev->dev, 1);
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if (!host)
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goto fail;
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ap = host->ports[0];
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if (type == 6580) {
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ap->ops = &qdi6580_port_ops;
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ap->pio_mask = 0x1F;
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ap->flags |= ATA_FLAG_SLAVE_POSS;
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} else {
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ap->ops = &qdi6500_port_ops;
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ap->pio_mask = 0x07; /* Actually PIO3 !IORDY is possible */
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ap->flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
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}
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ap->ioaddr.cmd_addr = io_addr;
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ap->ioaddr.altstatus_addr = ctl_addr;
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ap->ioaddr.ctl_addr = ctl_addr;
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ata_std_ports(&ap->ioaddr);
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ata_port_desc(ap, "cmd %lx ctl %lx", io, ctl);
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/*
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* Hook in a private data structure per channel
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*/
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ap->private_data = &qdi_data[nr_qdi_host];
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qdi_data[nr_qdi_host].timing = port;
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qdi_data[nr_qdi_host].fast = fast;
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qdi_data[nr_qdi_host].platform_dev = pdev;
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printk(KERN_INFO DRV_NAME": qd%d at 0x%lx.\n", type, io);
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/* activate */
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ret = ata_host_activate(host, irq, ata_interrupt, 0, &qdi_sht);
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if (ret)
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goto fail;
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qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev);
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return 0;
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fail:
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platform_device_unregister(pdev);
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return ret;
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}
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/**
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* qdi_init - attach qdi interfaces
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*
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* Attach qdi IDE interfaces by scanning the ports it may occupy.
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*/
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static __init int qdi_init(void)
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{
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unsigned long flags;
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static const unsigned long qd_port[2] = { 0x30, 0xB0 };
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static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
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static const int ide_irq[2] = { 14, 15 };
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int ct = 0;
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int i;
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if (probe_qdi == 0)
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return -ENODEV;
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/*
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* Check each possible QD65xx base address
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*/
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for (i = 0; i < 2; i++) {
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unsigned long port = qd_port[i];
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u8 r, res;
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if (request_region(port, 2, "pata_qdi")) {
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/* Check for a card */
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local_irq_save(flags);
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r = inb_p(port);
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outb_p(0x19, port);
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res = inb_p(port);
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outb_p(r, port);
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local_irq_restore(flags);
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/* Fail */
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if (res == 0x19)
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{
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release_region(port, 2);
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continue;
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}
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/* Passes the presence test */
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r = inb_p(port + 1); /* Check port agrees with port set */
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if ((r & 2) >> 1 != i) {
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release_region(port, 2);
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continue;
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}
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/* Check card type */
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if ((r & 0xF0) == 0xC0) {
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/* QD6500: single channel */
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if (r & 8) {
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/* Disabled ? */
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release_region(port, 2);
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continue;
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}
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if (qdi_init_one(port, 6500, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04) == 0)
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ct++;
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}
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if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
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/* QD6580: dual channel */
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if (!request_region(port + 2 , 2, "pata_qdi"))
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{
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release_region(port, 2);
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continue;
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}
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res = inb(port + 3);
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if (res & 1) {
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/* Single channel mode */
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if (qdi_init_one(port, 6580, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04) == 0)
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ct++;
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} else {
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/* Dual channel mode */
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if (qdi_init_one(port, 6580, 0x1F0, 14, r & 0x04) == 0)
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ct++;
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if (qdi_init_one(port + 2, 6580, 0x170, 15, r & 0x04) == 0)
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ct++;
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}
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}
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}
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}
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if (ct != 0)
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return 0;
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return -ENODEV;
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}
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static __exit void qdi_exit(void)
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{
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int i;
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for (i = 0; i < nr_qdi_host; i++) {
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ata_host_detach(qdi_host[i]);
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/* Free the control resource. The 6580 dual channel has the resources
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* claimed as a pair of 2 byte resources so we need no special cases...
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*/
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release_region(qdi_data[i].timing, 2);
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platform_device_unregister(qdi_data[i].platform_dev);
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}
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for qdi ATA");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_VERSION);
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module_init(qdi_init);
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module_exit(qdi_exit);
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module_param(probe_qdi, int, 0);
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