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463464eb9b
read_pll_ref() needs to take into account the refclk src bits in 0xc040 on some chipsets, it wasn't doing this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
687 lines
17 KiB
C
687 lines
17 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_bios.h"
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#include "nouveau_hw.h"
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#include "nouveau_pm.h"
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enum clk_src {
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clk_src_crystal,
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clk_src_href,
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clk_src_hclk,
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clk_src_hclkm3,
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clk_src_hclkm3d2,
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clk_src_host,
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clk_src_nvclk,
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clk_src_sclk,
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clk_src_mclk,
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clk_src_vdec,
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clk_src_dom6
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};
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static u32 read_clk(struct drm_device *, enum clk_src);
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static u32
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read_div(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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switch (dev_priv->chipset) {
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case 0x50: /* it exists, but only has bit 31, not the dividers.. */
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case 0x84:
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case 0x86:
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case 0x98:
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case 0xa0:
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return nv_rd32(dev, 0x004700);
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case 0x92:
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case 0x94:
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case 0x96:
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return nv_rd32(dev, 0x004800);
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default:
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return 0x00000000;
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}
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}
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static u32
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read_pll_src(struct drm_device *dev, u32 base)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 coef, ref = read_clk(dev, clk_src_crystal);
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u32 rsel = nv_rd32(dev, 0x00e18c);
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int P, N, M, id;
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switch (dev_priv->chipset) {
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case 0x50:
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case 0xa0:
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switch (base) {
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case 0x4020:
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case 0x4028: id = !!(rsel & 0x00000004); break;
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case 0x4008: id = !!(rsel & 0x00000008); break;
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case 0x4030: id = 0; break;
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default:
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NV_ERROR(dev, "ref: bad pll 0x%06x\n", base);
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return 0;
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}
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coef = nv_rd32(dev, 0x00e81c + (id * 0x0c));
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ref *= (coef & 0x01000000) ? 2 : 4;
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P = (coef & 0x00070000) >> 16;
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N = ((coef & 0x0000ff00) >> 8) + 1;
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M = ((coef & 0x000000ff) >> 0) + 1;
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break;
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case 0x84:
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case 0x86:
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case 0x92:
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coef = nv_rd32(dev, 0x00e81c);
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P = (coef & 0x00070000) >> 16;
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N = (coef & 0x0000ff00) >> 8;
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M = (coef & 0x000000ff) >> 0;
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break;
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case 0x94:
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case 0x96:
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case 0x98:
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rsel = nv_rd32(dev, 0x00c050);
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switch (base) {
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case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
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case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
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case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
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case 0x4030: rsel = 3; break;
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default:
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NV_ERROR(dev, "ref: bad pll 0x%06x\n", base);
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return 0;
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}
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switch (rsel) {
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case 0: id = 1; break;
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case 1: return read_clk(dev, clk_src_crystal);
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case 2: return read_clk(dev, clk_src_href);
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case 3: id = 0; break;
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}
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coef = nv_rd32(dev, 0x00e81c + (id * 0x28));
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P = (nv_rd32(dev, 0x00e824 + (id * 0x28)) >> 16) & 7;
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P += (coef & 0x00070000) >> 16;
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N = (coef & 0x0000ff00) >> 8;
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M = (coef & 0x000000ff) >> 0;
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break;
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default:
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BUG_ON(1);
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}
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if (M)
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return (ref * N / M) >> P;
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return 0;
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}
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static u32
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read_pll_ref(struct drm_device *dev, u32 base)
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{
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u32 src, mast = nv_rd32(dev, 0x00c040);
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switch (base) {
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case 0x004028:
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src = !!(mast & 0x00200000);
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break;
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case 0x004020:
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src = !!(mast & 0x00400000);
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break;
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case 0x004008:
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src = !!(mast & 0x00010000);
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break;
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case 0x004030:
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src = !!(mast & 0x02000000);
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break;
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case 0x00e810:
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return read_clk(dev, clk_src_crystal);
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default:
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NV_ERROR(dev, "bad pll 0x%06x\n", base);
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return 0;
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}
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if (src)
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return read_clk(dev, clk_src_href);
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return read_pll_src(dev, base);
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}
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static u32
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read_pll(struct drm_device *dev, u32 base)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 mast = nv_rd32(dev, 0x00c040);
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u32 ctrl = nv_rd32(dev, base + 0);
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u32 coef = nv_rd32(dev, base + 4);
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u32 ref = read_pll_ref(dev, base);
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u32 clk = 0;
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int N1, N2, M1, M2;
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if (base == 0x004028 && (mast & 0x00100000)) {
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/* wtf, appears to only disable post-divider on nva0 */
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if (dev_priv->chipset != 0xa0)
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return read_clk(dev, clk_src_dom6);
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}
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N2 = (coef & 0xff000000) >> 24;
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M2 = (coef & 0x00ff0000) >> 16;
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N1 = (coef & 0x0000ff00) >> 8;
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M1 = (coef & 0x000000ff);
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if ((ctrl & 0x80000000) && M1) {
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clk = ref * N1 / M1;
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if ((ctrl & 0x40000100) == 0x40000000) {
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if (M2)
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clk = clk * N2 / M2;
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else
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clk = 0;
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}
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}
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return clk;
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}
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static u32
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read_clk(struct drm_device *dev, enum clk_src src)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 mast = nv_rd32(dev, 0x00c040);
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u32 P = 0;
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switch (src) {
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case clk_src_crystal:
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return dev_priv->crystal;
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case clk_src_href:
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return 100000; /* PCIE reference clock */
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case clk_src_hclk:
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return read_clk(dev, clk_src_href) * 27778 / 10000;
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case clk_src_hclkm3:
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return read_clk(dev, clk_src_hclk) * 3;
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case clk_src_hclkm3d2:
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return read_clk(dev, clk_src_hclk) * 3 / 2;
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case clk_src_host:
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switch (mast & 0x30000000) {
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case 0x00000000: return read_clk(dev, clk_src_href);
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case 0x10000000: break;
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case 0x20000000: /* !0x50 */
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case 0x30000000: return read_clk(dev, clk_src_hclk);
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}
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break;
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case clk_src_nvclk:
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if (!(mast & 0x00100000))
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P = (nv_rd32(dev, 0x004028) & 0x00070000) >> 16;
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switch (mast & 0x00000003) {
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case 0x00000000: return read_clk(dev, clk_src_crystal) >> P;
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case 0x00000001: return read_clk(dev, clk_src_dom6);
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case 0x00000002: return read_pll(dev, 0x004020) >> P;
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case 0x00000003: return read_pll(dev, 0x004028) >> P;
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}
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break;
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case clk_src_sclk:
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P = (nv_rd32(dev, 0x004020) & 0x00070000) >> 16;
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switch (mast & 0x00000030) {
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case 0x00000000:
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if (mast & 0x00000080)
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return read_clk(dev, clk_src_host) >> P;
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return read_clk(dev, clk_src_crystal) >> P;
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case 0x00000010: break;
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case 0x00000020: return read_pll(dev, 0x004028) >> P;
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case 0x00000030: return read_pll(dev, 0x004020) >> P;
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}
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break;
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case clk_src_mclk:
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P = (nv_rd32(dev, 0x004008) & 0x00070000) >> 16;
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if (nv_rd32(dev, 0x004008) & 0x00000200) {
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switch (mast & 0x0000c000) {
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case 0x00000000:
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return read_clk(dev, clk_src_crystal) >> P;
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case 0x00008000:
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case 0x0000c000:
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return read_clk(dev, clk_src_href) >> P;
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}
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} else {
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return read_pll(dev, 0x004008) >> P;
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}
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break;
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case clk_src_vdec:
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P = (read_div(dev) & 0x00000700) >> 8;
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switch (dev_priv->chipset) {
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case 0x84:
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case 0x86:
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case 0x92:
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case 0x94:
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case 0x96:
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case 0xa0:
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switch (mast & 0x00000c00) {
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case 0x00000000:
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if (dev_priv->chipset == 0xa0) /* wtf?? */
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return read_clk(dev, clk_src_nvclk) >> P;
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return read_clk(dev, clk_src_crystal) >> P;
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case 0x00000400:
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return 0;
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case 0x00000800:
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if (mast & 0x01000000)
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return read_pll(dev, 0x004028) >> P;
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return read_pll(dev, 0x004030) >> P;
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case 0x00000c00:
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return read_clk(dev, clk_src_nvclk) >> P;
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}
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break;
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case 0x98:
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switch (mast & 0x00000c00) {
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case 0x00000000:
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return read_clk(dev, clk_src_nvclk) >> P;
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case 0x00000400:
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return 0;
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case 0x00000800:
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return read_clk(dev, clk_src_hclkm3d2) >> P;
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case 0x00000c00:
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return read_pll(dev, clk_src_mclk) >> P;
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}
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break;
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}
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break;
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case clk_src_dom6:
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switch (dev_priv->chipset) {
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case 0x50:
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case 0xa0:
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return read_pll(dev, 0x00e810) >> 2;
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case 0x84:
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case 0x86:
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case 0x92:
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case 0x94:
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case 0x96:
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case 0x98:
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P = (read_div(dev) & 0x00000007) >> 0;
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switch (mast & 0x0c000000) {
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case 0x00000000: return read_clk(dev, clk_src_href);
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case 0x04000000: break;
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case 0x08000000: return read_clk(dev, clk_src_hclk);
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case 0x0c000000:
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return read_clk(dev, clk_src_hclkm3) >> P;
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}
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break;
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default:
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break;
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}
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default:
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break;
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}
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NV_DEBUG(dev, "unknown clock source %d 0x%08x\n", src, mast);
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return 0;
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}
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int
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nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->chipset == 0xaa ||
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dev_priv->chipset == 0xac)
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return 0;
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perflvl->core = read_clk(dev, clk_src_nvclk);
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perflvl->shader = read_clk(dev, clk_src_sclk);
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perflvl->memory = read_clk(dev, clk_src_mclk);
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if (dev_priv->chipset != 0x50) {
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perflvl->vdec = read_clk(dev, clk_src_vdec);
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perflvl->dom6 = read_clk(dev, clk_src_dom6);
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}
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return 0;
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}
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struct nv50_pm_state {
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u32 emast;
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u32 nctrl;
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u32 ncoef;
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u32 sctrl;
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u32 scoef;
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u32 amast;
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u32 pdivs;
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u32 mscript;
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u32 mctrl;
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u32 mcoef;
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};
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static u32
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calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll,
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u32 clk, int *N1, int *M1, int *log2P)
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{
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struct nouveau_pll_vals coef;
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int ret;
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ret = get_pll_limits(dev, reg, pll);
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if (ret)
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return 0;
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pll->vco2.maxfreq = 0;
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pll->refclk = read_pll_ref(dev, reg);
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if (!pll->refclk)
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return 0;
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ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef);
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if (ret == 0)
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return 0;
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*N1 = coef.N1;
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*M1 = coef.M1;
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*log2P = coef.log2P;
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return ret;
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}
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static inline u32
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calc_div(u32 src, u32 target, int *div)
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{
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u32 clk0 = src, clk1 = src;
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for (*div = 0; *div <= 7; (*div)++) {
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if (clk0 <= target) {
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clk1 = clk0 << (*div ? 1 : 0);
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break;
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}
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clk0 >>= 1;
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}
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if (target - clk0 <= clk1 - target)
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return clk0;
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(*div)--;
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return clk1;
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}
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static inline u32
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clk_same(u32 a, u32 b)
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{
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return ((a / 1000) == (b / 1000));
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}
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void *
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nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_pm_state *info;
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struct pll_lims pll;
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int ret = -EINVAL;
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int N, M, P1, P2;
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u32 clk, out;
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if (dev_priv->chipset == 0xaa ||
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dev_priv->chipset == 0xac)
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return ERR_PTR(-ENODEV);
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info = kmalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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/* core: for the moment at least, always use nvpll */
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clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
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if (clk == 0)
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goto error;
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info->emast = 0x00000003;
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info->nctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
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info->ncoef = (N << 8) | M;
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/* shader: tie to nvclk if possible, otherwise use spll. have to be
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* very careful that the shader clock is at least twice the core, or
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* some chipsets will be very unhappy. i expect most or all of these
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* cases will be handled by tying to nvclk, but it's possible there's
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* corners
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*/
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if (P1-- && perflvl->shader == (perflvl->core << 1)) {
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info->emast |= 0x00000020;
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info->sctrl = 0x00000000 | (P1 << 19) | (P1 << 16);
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info->scoef = nv_rd32(dev, 0x004024);
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} else {
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clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
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if (clk == 0)
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goto error;
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info->emast |= 0x00000030;
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info->sctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
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info->scoef = (N << 8) | M;
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}
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/* memory: use pcie refclock if possible, otherwise use mpll */
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info->mscript = perflvl->memscript;
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if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
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info->mctrl = nv_rd32(dev, 0x4008) | 0x00000200;
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info->mcoef = nv_rd32(dev, 0x400c);
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} else
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if (perflvl->memory) {
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clk = calc_pll(dev, 0x4008, &pll, perflvl->memory,
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&N, &M, &P1);
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if (clk == 0)
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goto error;
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info->mctrl = 0x80000000 | (P1 << 22) | (P1 << 16);
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info->mctrl |= pll.log2p_bias << 19;
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info->mcoef = (N << 8) | M;
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} else {
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info->mctrl = 0x00000000;
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}
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/* vdec: avoid modifying xpll until we know exactly how the other
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* clock domains work, i suspect at least some of them can also be
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* tied to xpll...
|
|
*/
|
|
info->amast = info->pdivs = 0;
|
|
if (perflvl->vdec) {
|
|
/* see how close we can get using nvclk as a source */
|
|
clk = calc_div(perflvl->core, perflvl->vdec, &P1);
|
|
|
|
/* see how close we can get using xpll/hclk as a source */
|
|
if (dev_priv->chipset != 0x98)
|
|
out = read_pll(dev, 0x004030);
|
|
else
|
|
out = read_clk(dev, clk_src_hclkm3d2);
|
|
out = calc_div(out, perflvl->vdec, &P2);
|
|
|
|
/* select whichever gets us closest */
|
|
if (abs((int)perflvl->vdec - clk) <=
|
|
abs((int)perflvl->vdec - out)) {
|
|
if (dev_priv->chipset != 0x98)
|
|
info->amast |= 0x00000c00;
|
|
else
|
|
info->amast |= 0x00000000;
|
|
info->pdivs |= P1 << 8;
|
|
} else {
|
|
info->amast |= 0x00000800;
|
|
info->pdivs |= P2 << 8;
|
|
}
|
|
}
|
|
|
|
/* dom6: nfi what this is, but we're limited to various combinations
|
|
* of the host clock frequency
|
|
*/
|
|
if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) {
|
|
info->amast |= 0x00000000;
|
|
info->pdivs |= read_div(dev) & 0x00000007;
|
|
} else
|
|
if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) {
|
|
info->amast |= 0x08000000;
|
|
info->pdivs |= read_div(dev) & 0x00000007;
|
|
} else
|
|
if (perflvl->dom6) {
|
|
clk = read_clk(dev, clk_src_hclk) * 3;
|
|
clk = calc_div(clk, perflvl->dom6, &P1);
|
|
|
|
info->amast |= 0x0c000000;
|
|
info->pdivs |= P1;
|
|
}
|
|
|
|
|
|
return info;
|
|
error:
|
|
kfree(info);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
int
|
|
nv50_pm_clocks_set(struct drm_device *dev, void *data)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nv50_pm_state *info = data;
|
|
struct bit_entry M;
|
|
int ret = 0;
|
|
|
|
/* halt and idle execution engines */
|
|
nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
|
|
if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010))
|
|
goto error;
|
|
|
|
/* reclock vdec/dom6 */
|
|
nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000);
|
|
switch (dev_priv->chipset) {
|
|
case 0x92:
|
|
case 0x94:
|
|
case 0x96:
|
|
nv_mask(dev, 0x004800, 0x00000707, info->pdivs);
|
|
break;
|
|
default:
|
|
nv_mask(dev, 0x004700, 0x00000707, info->pdivs);
|
|
break;
|
|
}
|
|
nv_mask(dev, 0x00c040, 0x0c000c00, info->amast);
|
|
|
|
/* core/shader: make sure sclk/nvclk are disconnected from their
|
|
* plls (nvclk to dom6, sclk to hclk), modify the plls, and
|
|
* reconnect sclk/nvclk to their new clock source
|
|
*/
|
|
if (dev_priv->chipset < 0x92)
|
|
nv_mask(dev, 0x00c040, 0x001000b0, 0x00100080); /* grrr! */
|
|
else
|
|
nv_mask(dev, 0x00c040, 0x000000b3, 0x00000081);
|
|
nv_mask(dev, 0x004020, 0xc03f0100, info->sctrl);
|
|
nv_wr32(dev, 0x004024, info->scoef);
|
|
nv_mask(dev, 0x004028, 0xc03f0100, info->nctrl);
|
|
nv_wr32(dev, 0x00402c, info->ncoef);
|
|
nv_mask(dev, 0x00c040, 0x00100033, info->emast);
|
|
|
|
/* memory */
|
|
if (!info->mctrl)
|
|
goto resume;
|
|
|
|
/* execute some scripts that do ??? from the vbios.. */
|
|
if (!bit_table(dev, 'M', &M) && M.version == 1) {
|
|
if (M.length >= 6)
|
|
nouveau_bios_init_exec(dev, ROM16(M.data[5]));
|
|
if (M.length >= 8)
|
|
nouveau_bios_init_exec(dev, ROM16(M.data[7]));
|
|
if (M.length >= 10)
|
|
nouveau_bios_init_exec(dev, ROM16(M.data[9]));
|
|
nouveau_bios_init_exec(dev, info->mscript);
|
|
}
|
|
|
|
/* disable display */
|
|
nv_wr32(dev, 0x611200, 0x00003300);
|
|
udelay(100);
|
|
|
|
/* prepare ram for reclocking */
|
|
nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */
|
|
nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
|
|
nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
|
|
nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto-refresh */
|
|
nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */
|
|
|
|
/* modify mpll */
|
|
nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);
|
|
nv_mask(dev, 0x004008, 0x81ff0200, 0x00000200 | info->mctrl);
|
|
nv_wr32(dev, 0x00400c, info->mcoef);
|
|
udelay(100);
|
|
nv_mask(dev, 0x004008, 0x81ff0200, info->mctrl);
|
|
|
|
/* re-enable normal operation of memory controller */
|
|
nv_wr32(dev, 0x1002dc, 0x00000000);
|
|
nv_mask(dev, 0x100210, 0x80000000, 0x80000000);
|
|
udelay(100);
|
|
|
|
/* re-enable display */
|
|
nv_wr32(dev, 0x611200, 0x00003330);
|
|
|
|
goto resume;
|
|
error:
|
|
ret = -EBUSY;
|
|
resume:
|
|
nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
|
|
kfree(info);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
pwm_info(struct drm_device *dev, struct dcb_gpio_entry *gpio,
|
|
int *ctrl, int *line, int *indx)
|
|
{
|
|
if (gpio->line == 0x04) {
|
|
*ctrl = 0x00e100;
|
|
*line = 4;
|
|
*indx = 0;
|
|
} else
|
|
if (gpio->line == 0x09) {
|
|
*ctrl = 0x00e100;
|
|
*line = 9;
|
|
*indx = 1;
|
|
} else
|
|
if (gpio->line == 0x10) {
|
|
*ctrl = 0x00e28c;
|
|
*line = 0;
|
|
*indx = 0;
|
|
} else {
|
|
NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", gpio->line);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nv50_pm_pwm_get(struct drm_device *dev, struct dcb_gpio_entry *gpio,
|
|
u32 *divs, u32 *duty)
|
|
{
|
|
int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (nv_rd32(dev, ctrl) & (1 << line)) {
|
|
*divs = nv_rd32(dev, 0x00e114 + (id * 8));
|
|
*duty = nv_rd32(dev, 0x00e118 + (id * 8));
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
int
|
|
nv50_pm_pwm_set(struct drm_device *dev, struct dcb_gpio_entry *gpio,
|
|
u32 divs, u32 duty)
|
|
{
|
|
int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nv_mask(dev, ctrl, 0x00010001 << line, 0x00000001 << line);
|
|
nv_wr32(dev, 0x00e114 + (id * 8), divs);
|
|
nv_wr32(dev, 0x00e118 + (id * 8), duty | 0x80000000);
|
|
return 0;
|
|
}
|