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a87ea88d8f
The RTC is used on Malta to estimate the clock frequency of the CPU & optionally the GIC. However the kernel previously did not initialise the RTC, instead relying upon the bootloader having done so. In order to minimise dependencies which the kernel has upon the bootloader this patch causes the kernel to initialise the RTC itself prior to making use of it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6184/
217 lines
5.1 KiB
C
217 lines
5.1 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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#include <linux/i8253.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <asm/setup.h>
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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#include <asm/msc01_ic.h>
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#include <asm/gic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/maltaint.h>
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static int mips_cpu_timer_irq;
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static int mips_cpu_perf_irq;
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extern int cp0_perfcount_irq;
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static void mips_timer_dispatch(void)
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{
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do_IRQ(mips_cpu_timer_irq);
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}
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static void mips_perf_dispatch(void)
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{
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do_IRQ(mips_cpu_perf_irq);
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}
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static unsigned int freqround(unsigned int freq, unsigned int amount)
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{
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freq += amount;
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freq -= freq % (amount*2);
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return freq;
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}
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/*
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* Estimate CPU and GIC frequencies.
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*/
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static void __init estimate_frequencies(void)
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{
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unsigned long flags;
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unsigned int count, start;
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#ifdef CONFIG_IRQ_GIC
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unsigned int giccount = 0, gicstart = 0;
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#endif
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#if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
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unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
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/*
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* XXXKYMA: hardwire the CPU frequency to Host Freq/4
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*/
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count = (CONFIG_KVM_HOST_FREQ * 1000000) >> 3;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count *= 2;
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mips_hpt_frequency = count;
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return;
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#endif
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local_irq_save(flags);
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/* Start counter exactly on falling edge of update flag. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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/* Initialize counters. */
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start = read_c0_count();
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#ifdef CONFIG_IRQ_GIC
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if (gic_present)
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
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#endif
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/* Read counter exactly on falling edge of update flag. */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count();
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#ifdef CONFIG_IRQ_GIC
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if (gic_present)
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
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#endif
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local_irq_restore(flags);
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count -= start;
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mips_hpt_frequency = count;
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#ifdef CONFIG_IRQ_GIC
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if (gic_present) {
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giccount -= gicstart;
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gic_frequency = giccount;
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}
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#endif
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}
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void read_persistent_clock(struct timespec *ts)
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{
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ts->tv_sec = mc146818_get_cmos_time();
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ts->tv_nsec = 0;
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}
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static void __init plat_perf_setup(void)
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{
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
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mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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} else
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#endif
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if (cp0_perfcount_irq >= 0) {
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if (cpu_has_vint)
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set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
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mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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#ifdef CONFIG_SMP
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irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
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#endif
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}
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}
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unsigned int get_c0_compare_int(void)
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{
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
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mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
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} else
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#endif
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{
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if (cpu_has_vint)
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set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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return mips_cpu_timer_irq;
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}
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static void __init init_rtc(void)
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{
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/* stop the clock whilst setting it up */
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CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
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/* 32KHz time base */
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CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
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/* start the clock */
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CMOS_WRITE(RTC_24H, RTC_CONTROL);
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}
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void __init plat_time_init(void)
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{
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unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
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unsigned int freq;
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init_rtc();
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estimate_frequencies();
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freq = mips_hpt_frequency;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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freq *= 2;
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freq = freqround(freq, 5000);
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printk("CPU frequency %d.%02d MHz\n", freq/1000000,
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(freq%1000000)*100/1000000);
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mips_scroll_message();
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#ifdef CONFIG_I8253
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/* Only Malta has a PIT. */
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setup_pit_timer();
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#endif
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#ifdef CONFIG_IRQ_GIC
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if (gic_present) {
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freq = freqround(gic_frequency, 5000);
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printk("GIC frequency %d.%02d MHz\n", freq/1000000,
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(freq%1000000)*100/1000000);
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#ifdef CONFIG_CSRC_GIC
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gic_clocksource_init(gic_frequency);
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#endif
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}
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#endif
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plat_perf_setup();
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}
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