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1bf7067c6e
Pull locking updates from Ingo Molnar:
"The main changes are:
- 'qspinlock' support, enabled on x86: queued spinlocks - these are
now the spinlock variant used by x86 as they outperform ticket
spinlocks in every category. (Waiman Long)
- 'pvqspinlock' support on x86: paravirtualized variant of queued
spinlocks. (Waiman Long, Peter Zijlstra)
- 'qrwlock' support, enabled on x86: queued rwlocks. Similar to
queued spinlocks, they are now the variant used by x86:
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
- various lockdep fixlets
- various locking primitives cleanups, further WRITE_ONCE()
propagation"
* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
locking/lockdep: Remove hard coded array size dependency
locking/qrwlock: Don't contend with readers when setting _QW_WAITING
lockdep: Do not break user-visible string
locking/arch: Rename set_mb() to smp_store_mb()
locking/arch: Add WRITE_ONCE() to set_mb()
rtmutex: Warn if trylock is called from hard/softirq context
arch: Remove __ARCH_HAVE_CMPXCHG
locking/rtmutex: Drop usage of __HAVE_ARCH_CMPXCHG
locking/qrwlock: Rename QUEUE_RWLOCK to QUEUED_RWLOCKS
locking/pvqspinlock: Rename QUEUED_SPINLOCK to QUEUED_SPINLOCKS
locking/pvqspinlock: Replace xchg() by the more descriptive set_mb()
locking/pvqspinlock, x86: Enable PV qspinlock for Xen
locking/pvqspinlock, x86: Enable PV qspinlock for KVM
locking/pvqspinlock, x86: Implement the paravirt qspinlock call patching
locking/pvqspinlock: Implement simple paravirt support for the qspinlock
locking/qspinlock: Revert to test-and-set on hypervisors
locking/qspinlock: Use a simple write to grab the lock
locking/qspinlock: Optimize for smaller NR_CPUS
locking/qspinlock: Extract out code snippets for the next patch
locking/qspinlock: Add pending bit
...
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
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*/
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#ifndef _ASM_POWERPC_BARRIER_H
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#define _ASM_POWERPC_BARRIER_H
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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* read_barrier_depends() prevents data-dependent loads being reordered
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* across this point (nop on PPC).
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*
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* *mb() variants without smp_ prefix must order all types of memory
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* operations with one another. sync is the only instruction sufficient
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* to do this.
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*
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* For the smp_ barriers, ordering is for cacheable memory operations
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* only. We have to use the sync instruction for smp_mb(), since lwsync
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* doesn't order loads with respect to previous stores. Lwsync can be
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* used for smp_rmb() and smp_wmb().
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*
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* However, on CPUs that don't support lwsync, lwsync actually maps to a
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* heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#ifdef __SUBARCH_HAS_LWSYNC
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# define SMPWMB LWSYNC
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#else
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# define SMPWMB eieio
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#endif
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#define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
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#define dma_rmb() __lwsync()
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#define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
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#ifdef CONFIG_SMP
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#define smp_lwsync() __lwsync()
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#define smp_mb() mb()
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#define smp_rmb() __lwsync()
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#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
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#else
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#define smp_lwsync() barrier()
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif /* CONFIG_SMP */
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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/*
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* This is a barrier which prevents following instructions from being
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* started until the value of the argument x is known. For example, if
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* x is a variable loaded from memory, this prevents following
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* instructions from being executed until the load has been performed.
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*/
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#define data_barrier(x) \
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asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_lwsync(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_lwsync(); \
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___p1; \
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})
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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#define smp_mb__before_spinlock() smp_mb()
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#endif /* _ASM_POWERPC_BARRIER_H */
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