Vitaly Wool 44c9225729 RISC-V: enable XIP ... Introduce XIP (eXecute In Place) support for RISC-V platforms. It allows code to be executed directly from non-volatile storage directly addressable by the CPU, such as QSPI NOR flash which can be found on many RISC-V platforms. This makes way for significant optimization of RAM footprint. The XIP kernel is not compressed since it has to run directly from flash, so it will occupy more space on the non-volatile storage. The physical flash address used to link the kernel object files and for storing it has to be known at compile time and is represented by a Kconfig option. XIP on RISC-V will for the time being only work on MMU-enabled kernels. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> [Alex: Rebase on top of "Move kernel mapping outside the linear mapping" ] Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> [Palmer: disable XIP for allyesconfig] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-04-26 08:31:28 -07:00
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cacheflush.c	mm: reorder includes after introduction of linux/pgtable.h	2020-06-09 09:39:13 -07:00
context.c	RISC-V: Implement ASID allocator	2021-02-18 23:18:06 -08:00
extable.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
fault.c	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00
hugetlbpage.c	hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate	2020-06-03 20:09:46 -07:00
init.c	RISC-V: enable XIP	2021-04-26 08:31:28 -07:00
kasan_init.c	riscv: add __init section marker to some functions	2021-04-26 08:25:07 -07:00
Makefile	riscv: Fixup patch_text panic in ftrace	2021-01-14 15:09:04 -08:00
pageattr.c	RISC-V Patches for the 5.11 Merge Window, Part 1	2020-12-18 10:43:07 -08:00
physaddr.c	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00
ptdump.c	riscv: add __init section marker to some functions	2021-04-26 08:25:07 -07:00
tlbflush.c	RISC-V: Issue a tlb page flush if possible	2019-10-29 11:32:18 -07:00