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badc386869
SBI PMU extension defines a set of firmware events which can provide useful information to guests about the number of SBI calls. As hypervisor implements the SBI PMU extension, these firmware events correspond to ecall invocations between VS->HS mode. All other firmware events will always report zero if monitored as KVM doesn't implement them. This patch adds all the infrastructure required to support firmware events. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
634 lines
17 KiB
C
634 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 Rivos Inc
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*
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* Authors:
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* Atish Patra <atishp@rivosinc.com>
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*/
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#define pr_fmt(fmt) "riscv-kvm-pmu: " fmt
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/kvm_host.h>
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#include <linux/perf/riscv_pmu.h>
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#include <asm/csr.h>
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#include <asm/kvm_vcpu_sbi.h>
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#include <asm/kvm_vcpu_pmu.h>
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#include <linux/bitops.h>
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#define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs)
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#define get_event_type(x) (((x) & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16)
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#define get_event_code(x) ((x) & SBI_PMU_EVENT_IDX_CODE_MASK)
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static enum perf_hw_id hw_event_perf_map[SBI_PMU_HW_GENERAL_MAX] = {
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[SBI_PMU_HW_CPU_CYCLES] = PERF_COUNT_HW_CPU_CYCLES,
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[SBI_PMU_HW_INSTRUCTIONS] = PERF_COUNT_HW_INSTRUCTIONS,
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[SBI_PMU_HW_CACHE_REFERENCES] = PERF_COUNT_HW_CACHE_REFERENCES,
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[SBI_PMU_HW_CACHE_MISSES] = PERF_COUNT_HW_CACHE_MISSES,
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[SBI_PMU_HW_BRANCH_INSTRUCTIONS] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
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[SBI_PMU_HW_BRANCH_MISSES] = PERF_COUNT_HW_BRANCH_MISSES,
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[SBI_PMU_HW_BUS_CYCLES] = PERF_COUNT_HW_BUS_CYCLES,
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[SBI_PMU_HW_STALLED_CYCLES_FRONTEND] = PERF_COUNT_HW_STALLED_CYCLES_FRONTEND,
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[SBI_PMU_HW_STALLED_CYCLES_BACKEND] = PERF_COUNT_HW_STALLED_CYCLES_BACKEND,
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[SBI_PMU_HW_REF_CPU_CYCLES] = PERF_COUNT_HW_REF_CPU_CYCLES,
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};
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static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc)
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{
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u64 counter_val_mask = GENMASK(pmc->cinfo.width, 0);
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u64 sample_period;
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if (!pmc->counter_val)
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sample_period = counter_val_mask + 1;
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else
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sample_period = (-pmc->counter_val) & counter_val_mask;
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return sample_period;
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}
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static u32 kvm_pmu_get_perf_event_type(unsigned long eidx)
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{
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enum sbi_pmu_event_type etype = get_event_type(eidx);
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u32 type = PERF_TYPE_MAX;
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switch (etype) {
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case SBI_PMU_EVENT_TYPE_HW:
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type = PERF_TYPE_HARDWARE;
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break;
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case SBI_PMU_EVENT_TYPE_CACHE:
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type = PERF_TYPE_HW_CACHE;
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break;
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case SBI_PMU_EVENT_TYPE_RAW:
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case SBI_PMU_EVENT_TYPE_FW:
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type = PERF_TYPE_RAW;
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break;
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default:
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break;
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}
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return type;
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}
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static bool kvm_pmu_is_fw_event(unsigned long eidx)
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{
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return get_event_type(eidx) == SBI_PMU_EVENT_TYPE_FW;
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}
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static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc)
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{
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if (pmc->perf_event) {
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perf_event_disable(pmc->perf_event);
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perf_event_release_kernel(pmc->perf_event);
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pmc->perf_event = NULL;
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}
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}
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static u64 kvm_pmu_get_perf_event_hw_config(u32 sbi_event_code)
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{
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return hw_event_perf_map[sbi_event_code];
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}
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static u64 kvm_pmu_get_perf_event_cache_config(u32 sbi_event_code)
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{
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u64 config = U64_MAX;
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unsigned int cache_type, cache_op, cache_result;
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/* All the cache event masks lie within 0xFF. No separate masking is necessary */
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cache_type = (sbi_event_code & SBI_PMU_EVENT_CACHE_ID_CODE_MASK) >>
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SBI_PMU_EVENT_CACHE_ID_SHIFT;
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cache_op = (sbi_event_code & SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK) >>
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SBI_PMU_EVENT_CACHE_OP_SHIFT;
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cache_result = sbi_event_code & SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX ||
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cache_op >= PERF_COUNT_HW_CACHE_OP_MAX ||
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cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return config;
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config = cache_type | (cache_op << 8) | (cache_result << 16);
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return config;
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}
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static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data)
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{
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enum sbi_pmu_event_type etype = get_event_type(eidx);
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u32 ecode = get_event_code(eidx);
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u64 config = U64_MAX;
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switch (etype) {
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case SBI_PMU_EVENT_TYPE_HW:
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if (ecode < SBI_PMU_HW_GENERAL_MAX)
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config = kvm_pmu_get_perf_event_hw_config(ecode);
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break;
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case SBI_PMU_EVENT_TYPE_CACHE:
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config = kvm_pmu_get_perf_event_cache_config(ecode);
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break;
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case SBI_PMU_EVENT_TYPE_RAW:
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config = evt_data & RISCV_PMU_RAW_EVENT_MASK;
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break;
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case SBI_PMU_EVENT_TYPE_FW:
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if (ecode < SBI_PMU_FW_MAX)
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config = (1ULL << 63) | ecode;
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break;
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default:
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break;
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}
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return config;
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}
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static int kvm_pmu_get_fixed_pmc_index(unsigned long eidx)
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{
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u32 etype = kvm_pmu_get_perf_event_type(eidx);
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u32 ecode = get_event_code(eidx);
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if (etype != SBI_PMU_EVENT_TYPE_HW)
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return -EINVAL;
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if (ecode == SBI_PMU_HW_CPU_CYCLES)
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return 0;
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else if (ecode == SBI_PMU_HW_INSTRUCTIONS)
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return 2;
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else
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return -EINVAL;
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}
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static int kvm_pmu_get_programmable_pmc_index(struct kvm_pmu *kvpmu, unsigned long eidx,
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unsigned long cbase, unsigned long cmask)
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{
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int ctr_idx = -1;
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int i, pmc_idx;
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int min, max;
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if (kvm_pmu_is_fw_event(eidx)) {
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/* Firmware counters are mapped 1:1 starting from num_hw_ctrs for simplicity */
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min = kvpmu->num_hw_ctrs;
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max = min + kvpmu->num_fw_ctrs;
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} else {
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/* First 3 counters are reserved for fixed counters */
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min = 3;
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max = kvpmu->num_hw_ctrs;
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}
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for_each_set_bit(i, &cmask, BITS_PER_LONG) {
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pmc_idx = i + cbase;
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if ((pmc_idx >= min && pmc_idx < max) &&
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!test_bit(pmc_idx, kvpmu->pmc_in_use)) {
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ctr_idx = pmc_idx;
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break;
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}
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}
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return ctr_idx;
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}
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static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsigned long eidx,
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unsigned long cbase, unsigned long cmask)
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{
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int ret;
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/* Fixed counters need to be have fixed mapping as they have different width */
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ret = kvm_pmu_get_fixed_pmc_index(eidx);
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if (ret >= 0)
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return ret;
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return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask);
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}
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static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
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unsigned long *out_val)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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u64 enabled, running;
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int fevent_code;
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pmc = &kvpmu->pmc[cidx];
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if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
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fevent_code = get_event_code(pmc->event_idx);
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pmc->counter_val = kvpmu->fw_event[fevent_code].value;
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} else if (pmc->perf_event) {
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pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
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} else {
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return -EINVAL;
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}
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*out_val = pmc->counter_val;
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return 0;
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}
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static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned long ctr_base,
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unsigned long ctr_mask)
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{
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/* Make sure the we have a valid counter mask requested from the caller */
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if (!ctr_mask || (ctr_base + __fls(ctr_mask) >= kvm_pmu_num_counters(kvpmu)))
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return -EINVAL;
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return 0;
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}
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static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_event_attr *attr,
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unsigned long flags, unsigned long eidx, unsigned long evtdata)
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{
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struct perf_event *event;
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kvm_pmu_release_perf_event(pmc);
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attr->config = kvm_pmu_get_perf_event_config(eidx, evtdata);
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if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) {
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//TODO: Do we really want to clear the value in hardware counter
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pmc->counter_val = 0;
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}
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/*
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* Set the default sample_period for now. The guest specified value
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* will be updated in the start call.
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*/
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attr->sample_period = kvm_pmu_get_sample_period(pmc);
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event = perf_event_create_kernel_counter(attr, -1, current, NULL, pmc);
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if (IS_ERR(event)) {
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pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ERR(event));
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return PTR_ERR(event);
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}
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pmc->perf_event = event;
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if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
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perf_event_enable(pmc->perf_event);
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return 0;
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}
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int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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struct kvm_fw_event *fevent;
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if (!kvpmu || fid >= SBI_PMU_FW_MAX)
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return -EINVAL;
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fevent = &kvpmu->fw_event[fid];
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if (fevent->started)
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fevent->value++;
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return 0;
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}
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int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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int cidx, ret = KVM_INSN_CONTINUE_NEXT_SEPC;
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if (!kvpmu || !kvpmu->init_done) {
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/*
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* In absence of sscofpmf in the platform, the guest OS may use
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* the legacy PMU driver to read cycle/instret. In that case,
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* just return 0 to avoid any illegal trap. However, any other
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* hpmcounter access should result in illegal trap as they must
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* be access through SBI PMU only.
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*/
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if (csr_num == CSR_CYCLE || csr_num == CSR_INSTRET) {
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*val = 0;
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return ret;
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} else {
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return KVM_INSN_ILLEGAL_TRAP;
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}
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}
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/* The counter CSR are read only. Thus, any write should result in illegal traps */
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if (wr_mask)
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return KVM_INSN_ILLEGAL_TRAP;
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cidx = csr_num - CSR_CYCLE;
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if (pmu_ctr_read(vcpu, cidx, val) < 0)
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return KVM_INSN_ILLEGAL_TRAP;
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return ret;
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}
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int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu,
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struct kvm_vcpu_sbi_return *retdata)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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retdata->out_val = kvm_pmu_num_counters(kvpmu);
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return 0;
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}
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int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx,
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struct kvm_vcpu_sbi_return *retdata)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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if (cidx > RISCV_KVM_MAX_COUNTERS || cidx == 1) {
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retdata->err_val = SBI_ERR_INVALID_PARAM;
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return 0;
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}
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retdata->out_val = kvpmu->pmc[cidx].cinfo.value;
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return 0;
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}
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int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags, u64 ival,
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struct kvm_vcpu_sbi_return *retdata)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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int i, pmc_index, sbiret = 0;
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struct kvm_pmc *pmc;
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int fevent_code;
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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/* Start the counters that have been configured and requested by the guest */
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for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) {
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pmc_index = i + ctr_base;
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if (!test_bit(pmc_index, kvpmu->pmc_in_use))
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continue;
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pmc = &kvpmu->pmc[pmc_index];
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if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
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pmc->counter_val = ival;
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if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
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fevent_code = get_event_code(pmc->event_idx);
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if (fevent_code >= SBI_PMU_FW_MAX) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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/* Check if the counter was already started for some reason */
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if (kvpmu->fw_event[fevent_code].started) {
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sbiret = SBI_ERR_ALREADY_STARTED;
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continue;
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}
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kvpmu->fw_event[fevent_code].started = true;
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kvpmu->fw_event[fevent_code].value = pmc->counter_val;
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} else if (pmc->perf_event) {
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if (unlikely(pmc->started)) {
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sbiret = SBI_ERR_ALREADY_STARTED;
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continue;
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}
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perf_event_period(pmc->perf_event, kvm_pmu_get_sample_period(pmc));
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perf_event_enable(pmc->perf_event);
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pmc->started = true;
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} else {
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sbiret = SBI_ERR_INVALID_PARAM;
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}
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}
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out:
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retdata->err_val = sbiret;
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return 0;
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}
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int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
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unsigned long ctr_mask, unsigned long flags,
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struct kvm_vcpu_sbi_return *retdata)
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{
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struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
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int i, pmc_index, sbiret = 0;
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u64 enabled, running;
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struct kvm_pmc *pmc;
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int fevent_code;
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if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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/* Stop the counters that have been configured and requested by the guest */
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for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) {
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pmc_index = i + ctr_base;
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if (!test_bit(pmc_index, kvpmu->pmc_in_use))
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continue;
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pmc = &kvpmu->pmc[pmc_index];
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if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
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fevent_code = get_event_code(pmc->event_idx);
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if (fevent_code >= SBI_PMU_FW_MAX) {
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sbiret = SBI_ERR_INVALID_PARAM;
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goto out;
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}
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if (!kvpmu->fw_event[fevent_code].started)
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sbiret = SBI_ERR_ALREADY_STOPPED;
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kvpmu->fw_event[fevent_code].started = false;
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} else if (pmc->perf_event) {
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if (pmc->started) {
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/* Stop counting the counter */
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perf_event_disable(pmc->perf_event);
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pmc->started = false;
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} else {
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sbiret = SBI_ERR_ALREADY_STOPPED;
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}
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if (flags & SBI_PMU_STOP_FLAG_RESET) {
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/* Relase the counter if this is a reset request */
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pmc->counter_val += perf_event_read_value(pmc->perf_event,
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&enabled, &running);
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kvm_pmu_release_perf_event(pmc);
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}
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} else {
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sbiret = SBI_ERR_INVALID_PARAM;
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}
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if (flags & SBI_PMU_STOP_FLAG_RESET) {
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pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
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clear_bit(pmc_index, kvpmu->pmc_in_use);
|
|
}
|
|
}
|
|
|
|
out:
|
|
retdata->err_val = sbiret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_base,
|
|
unsigned long ctr_mask, unsigned long flags,
|
|
unsigned long eidx, u64 evtdata,
|
|
struct kvm_vcpu_sbi_return *retdata)
|
|
{
|
|
int ctr_idx, ret, sbiret = 0;
|
|
bool is_fevent;
|
|
unsigned long event_code;
|
|
u32 etype = kvm_pmu_get_perf_event_type(eidx);
|
|
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc = NULL;
|
|
struct perf_event_attr attr = {
|
|
.type = etype,
|
|
.size = sizeof(struct perf_event_attr),
|
|
.pinned = true,
|
|
/*
|
|
* It should never reach here if the platform doesn't support the sscofpmf
|
|
* extension as mode filtering won't work without it.
|
|
*/
|
|
.exclude_host = true,
|
|
.exclude_hv = true,
|
|
.exclude_user = !!(flags & SBI_PMU_CFG_FLAG_SET_UINH),
|
|
.exclude_kernel = !!(flags & SBI_PMU_CFG_FLAG_SET_SINH),
|
|
.config1 = RISCV_PMU_CONFIG1_GUEST_EVENTS,
|
|
};
|
|
|
|
if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) {
|
|
sbiret = SBI_ERR_INVALID_PARAM;
|
|
goto out;
|
|
}
|
|
|
|
event_code = get_event_code(eidx);
|
|
is_fevent = kvm_pmu_is_fw_event(eidx);
|
|
if (is_fevent && event_code >= SBI_PMU_FW_MAX) {
|
|
sbiret = SBI_ERR_NOT_SUPPORTED;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* SKIP_MATCH flag indicates the caller is aware of the assigned counter
|
|
* for this event. Just do a sanity check if it already marked used.
|
|
*/
|
|
if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) {
|
|
if (!test_bit(ctr_base + __ffs(ctr_mask), kvpmu->pmc_in_use)) {
|
|
sbiret = SBI_ERR_FAILURE;
|
|
goto out;
|
|
}
|
|
ctr_idx = ctr_base + __ffs(ctr_mask);
|
|
} else {
|
|
ctr_idx = pmu_get_pmc_index(kvpmu, eidx, ctr_base, ctr_mask);
|
|
if (ctr_idx < 0) {
|
|
sbiret = SBI_ERR_NOT_SUPPORTED;
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
pmc = &kvpmu->pmc[ctr_idx];
|
|
pmc->idx = ctr_idx;
|
|
|
|
if (is_fevent) {
|
|
if (flags & SBI_PMU_CFG_FLAG_AUTO_START)
|
|
kvpmu->fw_event[event_code].started = true;
|
|
} else {
|
|
ret = kvm_pmu_create_perf_event(pmc, &attr, flags, eidx, evtdata);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
set_bit(ctr_idx, kvpmu->pmc_in_use);
|
|
pmc->event_idx = eidx;
|
|
retdata->out_val = ctr_idx;
|
|
out:
|
|
retdata->err_val = sbiret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
|
|
struct kvm_vcpu_sbi_return *retdata)
|
|
{
|
|
int ret;
|
|
|
|
ret = pmu_ctr_read(vcpu, cidx, &retdata->out_val);
|
|
if (ret == -EINVAL)
|
|
retdata->err_val = SBI_ERR_INVALID_PARAM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
|
|
{
|
|
int i = 0, ret, num_hw_ctrs = 0, hpm_width = 0;
|
|
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc;
|
|
|
|
/*
|
|
* PMU functionality should be only available to guests if privilege mode
|
|
* filtering is available in the host. Otherwise, guest will always count
|
|
* events while the execution is in hypervisor mode.
|
|
*/
|
|
if (!riscv_isa_extension_available(NULL, SSCOFPMF))
|
|
return;
|
|
|
|
ret = riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs);
|
|
if (ret < 0 || !hpm_width || !num_hw_ctrs)
|
|
return;
|
|
|
|
/*
|
|
* Increase the number of hardware counters to offset the time counter.
|
|
*/
|
|
kvpmu->num_hw_ctrs = num_hw_ctrs + 1;
|
|
kvpmu->num_fw_ctrs = SBI_PMU_FW_MAX;
|
|
memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event));
|
|
|
|
if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) {
|
|
pr_warn_once("Limiting the hardware counters to 32 as specified by the ISA");
|
|
kvpmu->num_hw_ctrs = RISCV_KVM_MAX_HW_CTRS;
|
|
}
|
|
|
|
/*
|
|
* There is no correlation between the logical hardware counter and virtual counters.
|
|
* However, we need to encode a hpmcounter CSR in the counter info field so that
|
|
* KVM can trap n emulate the read. This works well in the migration use case as
|
|
* KVM doesn't care if the actual hpmcounter is available in the hardware or not.
|
|
*/
|
|
for (i = 0; i < kvm_pmu_num_counters(kvpmu); i++) {
|
|
/* TIME CSR shouldn't be read from perf interface */
|
|
if (i == 1)
|
|
continue;
|
|
pmc = &kvpmu->pmc[i];
|
|
pmc->idx = i;
|
|
pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
|
|
if (i < kvpmu->num_hw_ctrs) {
|
|
pmc->cinfo.type = SBI_PMU_CTR_TYPE_HW;
|
|
if (i < 3)
|
|
/* CY, IR counters */
|
|
pmc->cinfo.width = 63;
|
|
else
|
|
pmc->cinfo.width = hpm_width;
|
|
/*
|
|
* The CSR number doesn't have any relation with the logical
|
|
* hardware counters. The CSR numbers are encoded sequentially
|
|
* to avoid maintaining a map between the virtual counter
|
|
* and CSR number.
|
|
*/
|
|
pmc->cinfo.csr = CSR_CYCLE + i;
|
|
} else {
|
|
pmc->cinfo.type = SBI_PMU_CTR_TYPE_FW;
|
|
pmc->cinfo.width = BITS_PER_LONG - 1;
|
|
}
|
|
}
|
|
|
|
kvpmu->init_done = true;
|
|
}
|
|
|
|
void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc;
|
|
int i;
|
|
|
|
if (!kvpmu)
|
|
return;
|
|
|
|
for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) {
|
|
pmc = &kvpmu->pmc[i];
|
|
pmc->counter_val = 0;
|
|
kvm_pmu_release_perf_event(pmc);
|
|
pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
|
|
}
|
|
bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS);
|
|
memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event));
|
|
}
|
|
|
|
void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu)
|
|
{
|
|
kvm_riscv_vcpu_pmu_deinit(vcpu);
|
|
}
|