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d808f0b1be
The SEED CSR access from VS/VU mode (guest) will always trap to
HS-mode (KVM) when Zkr extension is available to the Guest/VM.
Forward this CSR access to KVM user space so that it can be
emulated based on the method chosen by VMM.
Fixes: f370b4e668
("RISC-V: KVM: Allow scalar crypto extensions for Guest/VM")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
768 lines
20 KiB
C
768 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/kvm_host.h>
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#include <asm/cpufeature.h>
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#define INSN_OPCODE_MASK 0x007c
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#define INSN_OPCODE_SHIFT 2
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#define INSN_OPCODE_SYSTEM 28
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#define INSN_MASK_WFI 0xffffffff
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#define INSN_MATCH_WFI 0x10500073
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#define INSN_MATCH_CSRRW 0x1073
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#define INSN_MASK_CSRRW 0x707f
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#define INSN_MATCH_CSRRS 0x2073
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#define INSN_MASK_CSRRS 0x707f
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#define INSN_MATCH_CSRRC 0x3073
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#define INSN_MASK_CSRRC 0x707f
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#define INSN_MATCH_CSRRWI 0x5073
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#define INSN_MASK_CSRRWI 0x707f
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#define INSN_MATCH_CSRRSI 0x6073
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#define INSN_MASK_CSRRSI 0x707f
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#define INSN_MATCH_CSRRCI 0x7073
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#define INSN_MASK_CSRRCI 0x707f
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#define INSN_MATCH_LB 0x3
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#define INSN_MASK_LB 0x707f
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#define INSN_MATCH_LH 0x1003
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#define INSN_MASK_LH 0x707f
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#define INSN_MATCH_LW 0x2003
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#define INSN_MASK_LW 0x707f
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#define INSN_MATCH_LD 0x3003
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#define INSN_MASK_LD 0x707f
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#define INSN_MATCH_LBU 0x4003
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#define INSN_MASK_LBU 0x707f
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#define INSN_MATCH_LHU 0x5003
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#define INSN_MASK_LHU 0x707f
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#define INSN_MATCH_LWU 0x6003
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#define INSN_MASK_LWU 0x707f
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#define INSN_MATCH_SB 0x23
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#define INSN_MASK_SB 0x707f
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#define INSN_MATCH_SH 0x1023
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#define INSN_MASK_SH 0x707f
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#define INSN_MATCH_SW 0x2023
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#define INSN_MASK_SW 0x707f
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#define INSN_MATCH_SD 0x3023
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#define INSN_MASK_SD 0x707f
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#define INSN_MATCH_C_LD 0x6000
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#define INSN_MASK_C_LD 0xe003
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#define INSN_MATCH_C_SD 0xe000
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#define INSN_MASK_C_SD 0xe003
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#define INSN_MATCH_C_LW 0x4000
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#define INSN_MASK_C_LW 0xe003
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#define INSN_MATCH_C_SW 0xc000
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#define INSN_MASK_C_SW 0xe003
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#define INSN_MATCH_C_LDSP 0x6002
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#define INSN_MASK_C_LDSP 0xe003
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#define INSN_MATCH_C_SDSP 0xe002
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#define INSN_MASK_C_SDSP 0xe003
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#define INSN_MATCH_C_LWSP 0x4002
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#define INSN_MASK_C_LWSP 0xe003
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#define INSN_MATCH_C_SWSP 0xc002
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#define INSN_MASK_C_SWSP 0xe003
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#define INSN_16BIT_MASK 0x3
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#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
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#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
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#ifdef CONFIG_64BIT
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#define LOG_REGBYTES 3
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#else
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#define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#define SH_RD 7
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#define SH_RS1 15
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#define SH_RS2 20
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#define SH_RS2C 2
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#define MASK_RX 0x1f
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
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(RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 1) << 6))
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#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 2) << 6))
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#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 2) << 6))
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#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 3) << 6))
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#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
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(RV_X(x, 7, 2) << 6))
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#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 7, 3) << 6))
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#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
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#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
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#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
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#define SHIFT_RIGHT(x, y) \
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((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
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#define REG_MASK \
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((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
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#define REG_OFFSET(insn, pos) \
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(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
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#define REG_PTR(insn, pos, regs) \
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((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
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#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
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#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
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#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
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#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
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#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
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#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
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#define GET_SP(regs) (*REG_PTR(2, 0, regs))
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#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
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#define IMM_I(insn) ((s32)(insn) >> 20)
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#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
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(s32)(((insn) >> 7) & 0x1f))
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struct insn_func {
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unsigned long mask;
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unsigned long match;
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/*
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* Possible return values are as follows:
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* 1) Returns < 0 for error case
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* 2) Returns 0 for exit to user-space
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* 3) Returns 1 to continue with next sepc
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* 4) Returns 2 to continue with same sepc
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* 5) Returns 3 to inject illegal instruction trap and continue
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* 6) Returns 4 to inject virtual instruction trap and continue
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*
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* Use enum kvm_insn_return for return values
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*/
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int (*func)(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn);
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};
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static int truly_illegal_insn(struct kvm_vcpu *vcpu, struct kvm_run *run,
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ulong insn)
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{
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struct kvm_cpu_trap utrap = { 0 };
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/* Redirect trap to Guest VCPU */
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utrap.sepc = vcpu->arch.guest_context.sepc;
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utrap.scause = EXC_INST_ILLEGAL;
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utrap.stval = insn;
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utrap.htval = 0;
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utrap.htinst = 0;
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kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
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return 1;
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}
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static int truly_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run,
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ulong insn)
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{
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struct kvm_cpu_trap utrap = { 0 };
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/* Redirect trap to Guest VCPU */
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utrap.sepc = vcpu->arch.guest_context.sepc;
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utrap.scause = EXC_VIRTUAL_INST_FAULT;
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utrap.stval = insn;
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utrap.htval = 0;
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utrap.htinst = 0;
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kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
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return 1;
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}
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/**
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* kvm_riscv_vcpu_wfi -- Emulate wait for interrupt (WFI) behaviour
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*
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* @vcpu: The VCPU pointer
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*/
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void kvm_riscv_vcpu_wfi(struct kvm_vcpu *vcpu)
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{
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if (!kvm_arch_vcpu_runnable(vcpu)) {
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kvm_vcpu_srcu_read_unlock(vcpu);
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kvm_vcpu_halt(vcpu);
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kvm_vcpu_srcu_read_lock(vcpu);
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}
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}
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static int wfi_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn)
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{
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vcpu->stat.wfi_exit_stat++;
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kvm_riscv_vcpu_wfi(vcpu);
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return KVM_INSN_CONTINUE_NEXT_SEPC;
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}
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struct csr_func {
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unsigned int base;
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unsigned int count;
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/*
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* Possible return values are as same as "func" callback in
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* "struct insn_func".
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*/
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int (*func)(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask);
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};
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static int seed_csr_rmw(struct kvm_vcpu *vcpu, unsigned int csr_num,
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unsigned long *val, unsigned long new_val,
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unsigned long wr_mask)
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{
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZKR))
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return KVM_INSN_ILLEGAL_TRAP;
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return KVM_INSN_EXIT_TO_USER_SPACE;
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}
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static const struct csr_func csr_funcs[] = {
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KVM_RISCV_VCPU_AIA_CSR_FUNCS
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KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS
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{ .base = CSR_SEED, .count = 1, .func = seed_csr_rmw },
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};
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/**
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* kvm_riscv_vcpu_csr_return -- Handle CSR read/write after user space
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* emulation or in-kernel emulation
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*
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* @vcpu: The VCPU pointer
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* @run: The VCPU run struct containing the CSR data
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*
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* Returns > 0 upon failure and 0 upon success
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*/
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int kvm_riscv_vcpu_csr_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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ulong insn;
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if (vcpu->arch.csr_decode.return_handled)
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return 0;
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vcpu->arch.csr_decode.return_handled = 1;
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/* Update destination register for CSR reads */
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insn = vcpu->arch.csr_decode.insn;
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if ((insn >> SH_RD) & MASK_RX)
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SET_RD(insn, &vcpu->arch.guest_context,
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run->riscv_csr.ret_value);
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/* Move to next instruction */
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vcpu->arch.guest_context.sepc += INSN_LEN(insn);
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return 0;
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}
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static int csr_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn)
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{
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int i, rc = KVM_INSN_ILLEGAL_TRAP;
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unsigned int csr_num = insn >> SH_RS2;
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unsigned int rs1_num = (insn >> SH_RS1) & MASK_RX;
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ulong rs1_val = GET_RS1(insn, &vcpu->arch.guest_context);
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const struct csr_func *tcfn, *cfn = NULL;
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ulong val = 0, wr_mask = 0, new_val = 0;
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/* Decode the CSR instruction */
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switch (GET_FUNCT3(insn)) {
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case GET_FUNCT3(INSN_MATCH_CSRRW):
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wr_mask = -1UL;
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new_val = rs1_val;
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break;
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case GET_FUNCT3(INSN_MATCH_CSRRS):
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wr_mask = rs1_val;
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new_val = -1UL;
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break;
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case GET_FUNCT3(INSN_MATCH_CSRRC):
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wr_mask = rs1_val;
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new_val = 0;
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break;
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case GET_FUNCT3(INSN_MATCH_CSRRWI):
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wr_mask = -1UL;
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new_val = rs1_num;
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break;
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case GET_FUNCT3(INSN_MATCH_CSRRSI):
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wr_mask = rs1_num;
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new_val = -1UL;
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break;
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case GET_FUNCT3(INSN_MATCH_CSRRCI):
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wr_mask = rs1_num;
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new_val = 0;
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break;
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default:
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return rc;
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}
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/* Save instruction decode info */
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vcpu->arch.csr_decode.insn = insn;
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vcpu->arch.csr_decode.return_handled = 0;
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/* Update CSR details in kvm_run struct */
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run->riscv_csr.csr_num = csr_num;
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run->riscv_csr.new_value = new_val;
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run->riscv_csr.write_mask = wr_mask;
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run->riscv_csr.ret_value = 0;
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/* Find in-kernel CSR function */
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for (i = 0; i < ARRAY_SIZE(csr_funcs); i++) {
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tcfn = &csr_funcs[i];
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if ((tcfn->base <= csr_num) &&
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(csr_num < (tcfn->base + tcfn->count))) {
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cfn = tcfn;
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break;
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}
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}
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/* First try in-kernel CSR emulation */
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if (cfn && cfn->func) {
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rc = cfn->func(vcpu, csr_num, &val, new_val, wr_mask);
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if (rc > KVM_INSN_EXIT_TO_USER_SPACE) {
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if (rc == KVM_INSN_CONTINUE_NEXT_SEPC) {
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run->riscv_csr.ret_value = val;
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vcpu->stat.csr_exit_kernel++;
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kvm_riscv_vcpu_csr_return(vcpu, run);
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rc = KVM_INSN_CONTINUE_SAME_SEPC;
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}
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return rc;
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}
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}
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/* Exit to user-space for CSR emulation */
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if (rc <= KVM_INSN_EXIT_TO_USER_SPACE) {
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vcpu->stat.csr_exit_user++;
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run->exit_reason = KVM_EXIT_RISCV_CSR;
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}
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return rc;
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}
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static const struct insn_func system_opcode_funcs[] = {
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{
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.mask = INSN_MASK_CSRRW,
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.match = INSN_MATCH_CSRRW,
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.func = csr_insn,
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},
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{
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.mask = INSN_MASK_CSRRS,
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.match = INSN_MATCH_CSRRS,
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.func = csr_insn,
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},
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{
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.mask = INSN_MASK_CSRRC,
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.match = INSN_MATCH_CSRRC,
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.func = csr_insn,
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},
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{
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.mask = INSN_MASK_CSRRWI,
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.match = INSN_MATCH_CSRRWI,
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.func = csr_insn,
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},
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{
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.mask = INSN_MASK_CSRRSI,
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.match = INSN_MATCH_CSRRSI,
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.func = csr_insn,
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},
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{
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.mask = INSN_MASK_CSRRCI,
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.match = INSN_MATCH_CSRRCI,
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.func = csr_insn,
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},
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{
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.mask = INSN_MASK_WFI,
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.match = INSN_MATCH_WFI,
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.func = wfi_insn,
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},
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};
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static int system_opcode_insn(struct kvm_vcpu *vcpu, struct kvm_run *run,
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ulong insn)
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{
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int i, rc = KVM_INSN_ILLEGAL_TRAP;
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const struct insn_func *ifn;
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for (i = 0; i < ARRAY_SIZE(system_opcode_funcs); i++) {
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ifn = &system_opcode_funcs[i];
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if ((insn & ifn->mask) == ifn->match) {
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rc = ifn->func(vcpu, run, insn);
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break;
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}
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}
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switch (rc) {
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case KVM_INSN_ILLEGAL_TRAP:
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return truly_illegal_insn(vcpu, run, insn);
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case KVM_INSN_VIRTUAL_TRAP:
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return truly_virtual_insn(vcpu, run, insn);
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case KVM_INSN_CONTINUE_NEXT_SEPC:
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vcpu->arch.guest_context.sepc += INSN_LEN(insn);
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break;
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default:
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break;
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}
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return (rc <= 0) ? rc : 1;
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}
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/**
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* kvm_riscv_vcpu_virtual_insn -- Handle virtual instruction trap
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*
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* @vcpu: The VCPU pointer
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* @run: The VCPU run struct containing the mmio data
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* @trap: Trap details
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*
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* Returns > 0 to continue run-loop
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* Returns 0 to exit run-loop and handle in user-space.
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* Returns < 0 to report failure and exit run-loop
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*/
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int kvm_riscv_vcpu_virtual_insn(struct kvm_vcpu *vcpu, struct kvm_run *run,
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struct kvm_cpu_trap *trap)
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{
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unsigned long insn = trap->stval;
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struct kvm_cpu_trap utrap = { 0 };
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struct kvm_cpu_context *ct;
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if (unlikely(INSN_IS_16BIT(insn))) {
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if (insn == 0) {
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ct = &vcpu->arch.guest_context;
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insn = kvm_riscv_vcpu_unpriv_read(vcpu, true,
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ct->sepc,
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&utrap);
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if (utrap.scause) {
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utrap.sepc = ct->sepc;
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kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
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return 1;
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}
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}
|
|
if (INSN_IS_16BIT(insn))
|
|
return truly_illegal_insn(vcpu, run, insn);
|
|
}
|
|
|
|
switch ((insn & INSN_OPCODE_MASK) >> INSN_OPCODE_SHIFT) {
|
|
case INSN_OPCODE_SYSTEM:
|
|
return system_opcode_insn(vcpu, run, insn);
|
|
default:
|
|
return truly_illegal_insn(vcpu, run, insn);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* kvm_riscv_vcpu_mmio_load -- Emulate MMIO load instruction
|
|
*
|
|
* @vcpu: The VCPU pointer
|
|
* @run: The VCPU run struct containing the mmio data
|
|
* @fault_addr: Guest physical address to load
|
|
* @htinst: Transformed encoding of the load instruction
|
|
*
|
|
* Returns > 0 to continue run-loop
|
|
* Returns 0 to exit run-loop and handle in user-space.
|
|
* Returns < 0 to report failure and exit run-loop
|
|
*/
|
|
int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
|
unsigned long fault_addr,
|
|
unsigned long htinst)
|
|
{
|
|
u8 data_buf[8];
|
|
unsigned long insn;
|
|
int shift = 0, len = 0, insn_len = 0;
|
|
struct kvm_cpu_trap utrap = { 0 };
|
|
struct kvm_cpu_context *ct = &vcpu->arch.guest_context;
|
|
|
|
/* Determine trapped instruction */
|
|
if (htinst & 0x1) {
|
|
/*
|
|
* Bit[0] == 1 implies trapped instruction value is
|
|
* transformed instruction or custom instruction.
|
|
*/
|
|
insn = htinst | INSN_16BIT_MASK;
|
|
insn_len = (htinst & BIT(1)) ? INSN_LEN(insn) : 2;
|
|
} else {
|
|
/*
|
|
* Bit[0] == 0 implies trapped instruction value is
|
|
* zero or special value.
|
|
*/
|
|
insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, ct->sepc,
|
|
&utrap);
|
|
if (utrap.scause) {
|
|
/* Redirect trap if we failed to read instruction */
|
|
utrap.sepc = ct->sepc;
|
|
kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
|
|
return 1;
|
|
}
|
|
insn_len = INSN_LEN(insn);
|
|
}
|
|
|
|
/* Decode length of MMIO and shift */
|
|
if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
|
|
len = 4;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
} else if ((insn & INSN_MASK_LB) == INSN_MATCH_LB) {
|
|
len = 1;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
} else if ((insn & INSN_MASK_LBU) == INSN_MATCH_LBU) {
|
|
len = 1;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
#ifdef CONFIG_64BIT
|
|
} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
|
|
len = 8;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
|
|
len = 4;
|
|
#endif
|
|
} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
|
|
len = 2;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
|
|
len = 2;
|
|
#ifdef CONFIG_64BIT
|
|
} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
|
|
len = 8;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
insn = RVC_RS2S(insn) << SH_RD;
|
|
} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
|
|
((insn >> SH_RD) & 0x1f)) {
|
|
len = 8;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
#endif
|
|
} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
|
|
len = 4;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
insn = RVC_RS2S(insn) << SH_RD;
|
|
} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
|
|
((insn >> SH_RD) & 0x1f)) {
|
|
len = 4;
|
|
shift = 8 * (sizeof(ulong) - len);
|
|
} else {
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
/* Fault address should be aligned to length of MMIO */
|
|
if (fault_addr & (len - 1))
|
|
return -EIO;
|
|
|
|
/* Save instruction decode info */
|
|
vcpu->arch.mmio_decode.insn = insn;
|
|
vcpu->arch.mmio_decode.insn_len = insn_len;
|
|
vcpu->arch.mmio_decode.shift = shift;
|
|
vcpu->arch.mmio_decode.len = len;
|
|
vcpu->arch.mmio_decode.return_handled = 0;
|
|
|
|
/* Update MMIO details in kvm_run struct */
|
|
run->mmio.is_write = false;
|
|
run->mmio.phys_addr = fault_addr;
|
|
run->mmio.len = len;
|
|
|
|
/* Try to handle MMIO access in the kernel */
|
|
if (!kvm_io_bus_read(vcpu, KVM_MMIO_BUS, fault_addr, len, data_buf)) {
|
|
/* Successfully handled MMIO access in the kernel so resume */
|
|
memcpy(run->mmio.data, data_buf, len);
|
|
vcpu->stat.mmio_exit_kernel++;
|
|
kvm_riscv_vcpu_mmio_return(vcpu, run);
|
|
return 1;
|
|
}
|
|
|
|
/* Exit to userspace for MMIO emulation */
|
|
vcpu->stat.mmio_exit_user++;
|
|
run->exit_reason = KVM_EXIT_MMIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* kvm_riscv_vcpu_mmio_store -- Emulate MMIO store instruction
|
|
*
|
|
* @vcpu: The VCPU pointer
|
|
* @run: The VCPU run struct containing the mmio data
|
|
* @fault_addr: Guest physical address to store
|
|
* @htinst: Transformed encoding of the store instruction
|
|
*
|
|
* Returns > 0 to continue run-loop
|
|
* Returns 0 to exit run-loop and handle in user-space.
|
|
* Returns < 0 to report failure and exit run-loop
|
|
*/
|
|
int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,
|
|
unsigned long fault_addr,
|
|
unsigned long htinst)
|
|
{
|
|
u8 data8;
|
|
u16 data16;
|
|
u32 data32;
|
|
u64 data64;
|
|
ulong data;
|
|
unsigned long insn;
|
|
int len = 0, insn_len = 0;
|
|
struct kvm_cpu_trap utrap = { 0 };
|
|
struct kvm_cpu_context *ct = &vcpu->arch.guest_context;
|
|
|
|
/* Determine trapped instruction */
|
|
if (htinst & 0x1) {
|
|
/*
|
|
* Bit[0] == 1 implies trapped instruction value is
|
|
* transformed instruction or custom instruction.
|
|
*/
|
|
insn = htinst | INSN_16BIT_MASK;
|
|
insn_len = (htinst & BIT(1)) ? INSN_LEN(insn) : 2;
|
|
} else {
|
|
/*
|
|
* Bit[0] == 0 implies trapped instruction value is
|
|
* zero or special value.
|
|
*/
|
|
insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, ct->sepc,
|
|
&utrap);
|
|
if (utrap.scause) {
|
|
/* Redirect trap if we failed to read instruction */
|
|
utrap.sepc = ct->sepc;
|
|
kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
|
|
return 1;
|
|
}
|
|
insn_len = INSN_LEN(insn);
|
|
}
|
|
|
|
data = GET_RS2(insn, &vcpu->arch.guest_context);
|
|
data8 = data16 = data32 = data64 = data;
|
|
|
|
if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
|
|
len = 4;
|
|
} else if ((insn & INSN_MASK_SB) == INSN_MATCH_SB) {
|
|
len = 1;
|
|
#ifdef CONFIG_64BIT
|
|
} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
|
|
len = 8;
|
|
#endif
|
|
} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
|
|
len = 2;
|
|
#ifdef CONFIG_64BIT
|
|
} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
|
|
len = 8;
|
|
data64 = GET_RS2S(insn, &vcpu->arch.guest_context);
|
|
} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
|
|
((insn >> SH_RD) & 0x1f)) {
|
|
len = 8;
|
|
data64 = GET_RS2C(insn, &vcpu->arch.guest_context);
|
|
#endif
|
|
} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
|
|
len = 4;
|
|
data32 = GET_RS2S(insn, &vcpu->arch.guest_context);
|
|
} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
|
|
((insn >> SH_RD) & 0x1f)) {
|
|
len = 4;
|
|
data32 = GET_RS2C(insn, &vcpu->arch.guest_context);
|
|
} else {
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
/* Fault address should be aligned to length of MMIO */
|
|
if (fault_addr & (len - 1))
|
|
return -EIO;
|
|
|
|
/* Save instruction decode info */
|
|
vcpu->arch.mmio_decode.insn = insn;
|
|
vcpu->arch.mmio_decode.insn_len = insn_len;
|
|
vcpu->arch.mmio_decode.shift = 0;
|
|
vcpu->arch.mmio_decode.len = len;
|
|
vcpu->arch.mmio_decode.return_handled = 0;
|
|
|
|
/* Copy data to kvm_run instance */
|
|
switch (len) {
|
|
case 1:
|
|
*((u8 *)run->mmio.data) = data8;
|
|
break;
|
|
case 2:
|
|
*((u16 *)run->mmio.data) = data16;
|
|
break;
|
|
case 4:
|
|
*((u32 *)run->mmio.data) = data32;
|
|
break;
|
|
case 8:
|
|
*((u64 *)run->mmio.data) = data64;
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
/* Update MMIO details in kvm_run struct */
|
|
run->mmio.is_write = true;
|
|
run->mmio.phys_addr = fault_addr;
|
|
run->mmio.len = len;
|
|
|
|
/* Try to handle MMIO access in the kernel */
|
|
if (!kvm_io_bus_write(vcpu, KVM_MMIO_BUS,
|
|
fault_addr, len, run->mmio.data)) {
|
|
/* Successfully handled MMIO access in the kernel so resume */
|
|
vcpu->stat.mmio_exit_kernel++;
|
|
kvm_riscv_vcpu_mmio_return(vcpu, run);
|
|
return 1;
|
|
}
|
|
|
|
/* Exit to userspace for MMIO emulation */
|
|
vcpu->stat.mmio_exit_user++;
|
|
run->exit_reason = KVM_EXIT_MMIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* kvm_riscv_vcpu_mmio_return -- Handle MMIO loads after user space emulation
|
|
* or in-kernel IO emulation
|
|
*
|
|
* @vcpu: The VCPU pointer
|
|
* @run: The VCPU run struct containing the mmio data
|
|
*/
|
|
int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
|
{
|
|
u8 data8;
|
|
u16 data16;
|
|
u32 data32;
|
|
u64 data64;
|
|
ulong insn;
|
|
int len, shift;
|
|
|
|
if (vcpu->arch.mmio_decode.return_handled)
|
|
return 0;
|
|
|
|
vcpu->arch.mmio_decode.return_handled = 1;
|
|
insn = vcpu->arch.mmio_decode.insn;
|
|
|
|
if (run->mmio.is_write)
|
|
goto done;
|
|
|
|
len = vcpu->arch.mmio_decode.len;
|
|
shift = vcpu->arch.mmio_decode.shift;
|
|
|
|
switch (len) {
|
|
case 1:
|
|
data8 = *((u8 *)run->mmio.data);
|
|
SET_RD(insn, &vcpu->arch.guest_context,
|
|
(ulong)data8 << shift >> shift);
|
|
break;
|
|
case 2:
|
|
data16 = *((u16 *)run->mmio.data);
|
|
SET_RD(insn, &vcpu->arch.guest_context,
|
|
(ulong)data16 << shift >> shift);
|
|
break;
|
|
case 4:
|
|
data32 = *((u32 *)run->mmio.data);
|
|
SET_RD(insn, &vcpu->arch.guest_context,
|
|
(ulong)data32 << shift >> shift);
|
|
break;
|
|
case 8:
|
|
data64 = *((u64 *)run->mmio.data);
|
|
SET_RD(insn, &vcpu->arch.guest_context,
|
|
(ulong)data64 << shift >> shift);
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
done:
|
|
/* Move to next instruction */
|
|
vcpu->arch.guest_context.sepc += vcpu->arch.mmio_decode.insn_len;
|
|
|
|
return 0;
|
|
}
|