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38b3390ee4
KVM's implementation of SBI STA needs to track the address of each VCPU's steal-time shared memory region as well as the amount of stolen time. Add a structure to vcpu_arch to contain this state and make sure that the address is always set to INVALID_GPA on vcpu reset. And, of course, ensure KVM won't try to update steal- time when the shared memory address is invalid. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
838 lines
21 KiB
C
838 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <linux/bitops.h>
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#include <linux/entry-kvm.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/kdebug.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/vmalloc.h>
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#include <linux/sched/signal.h>
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#include <linux/fs.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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#include <asm/cacheflush.h>
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#include <asm/kvm_vcpu_vector.h>
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const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
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KVM_GENERIC_VCPU_STATS(),
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STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
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STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
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STATS_DESC_COUNTER(VCPU, mmio_exit_user),
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STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
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STATS_DESC_COUNTER(VCPU, csr_exit_user),
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STATS_DESC_COUNTER(VCPU, csr_exit_kernel),
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STATS_DESC_COUNTER(VCPU, signal_exits),
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STATS_DESC_COUNTER(VCPU, exits)
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};
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const struct kvm_stats_header kvm_vcpu_stats_header = {
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.name_size = KVM_STATS_NAME_SIZE,
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.num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
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.id_offset = sizeof(struct kvm_stats_header),
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.desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
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.data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
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sizeof(kvm_vcpu_stats_desc),
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};
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static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context;
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bool loaded;
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/**
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* The preemption should be disabled here because it races with
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* kvm_sched_out/kvm_sched_in(called from preempt notifiers) which
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* also calls vcpu_load/put.
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*/
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get_cpu();
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loaded = (vcpu->cpu != -1);
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if (loaded)
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kvm_arch_vcpu_put(vcpu);
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vcpu->arch.last_exit_cpu = -1;
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memcpy(csr, reset_csr, sizeof(*csr));
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memcpy(cntx, reset_cntx, sizeof(*cntx));
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kvm_riscv_vcpu_fp_reset(vcpu);
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kvm_riscv_vcpu_vector_reset(vcpu);
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kvm_riscv_vcpu_timer_reset(vcpu);
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kvm_riscv_vcpu_aia_reset(vcpu);
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bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS);
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bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS);
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kvm_riscv_vcpu_pmu_reset(vcpu);
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vcpu->arch.hfence_head = 0;
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vcpu->arch.hfence_tail = 0;
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memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue));
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kvm_riscv_vcpu_sbi_sta_reset(vcpu);
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/* Reset the guest CSRs for hotplug usecase */
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if (loaded)
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kvm_arch_vcpu_load(vcpu, smp_processor_id());
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put_cpu();
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}
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int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
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{
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return 0;
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}
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int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
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{
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int rc;
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struct kvm_cpu_context *cntx;
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struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
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/* Mark this VCPU never ran */
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vcpu->arch.ran_atleast_once = false;
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vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO;
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bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX);
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/* Setup ISA features available to VCPU */
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kvm_riscv_vcpu_setup_isa(vcpu);
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/* Setup vendor, arch, and implementation details */
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vcpu->arch.mvendorid = sbi_get_mvendorid();
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vcpu->arch.marchid = sbi_get_marchid();
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vcpu->arch.mimpid = sbi_get_mimpid();
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/* Setup VCPU hfence queue */
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spin_lock_init(&vcpu->arch.hfence_lock);
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/* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
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cntx = &vcpu->arch.guest_reset_context;
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cntx->sstatus = SR_SPP | SR_SPIE;
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cntx->hstatus = 0;
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cntx->hstatus |= HSTATUS_VTW;
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cntx->hstatus |= HSTATUS_SPVP;
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cntx->hstatus |= HSTATUS_SPV;
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if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx))
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return -ENOMEM;
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/* By default, make CY, TM, and IR counters accessible in VU mode */
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reset_csr->scounteren = 0x7;
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/* Setup VCPU timer */
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kvm_riscv_vcpu_timer_init(vcpu);
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/* setup performance monitoring */
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kvm_riscv_vcpu_pmu_init(vcpu);
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/* Setup VCPU AIA */
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rc = kvm_riscv_vcpu_aia_init(vcpu);
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if (rc)
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return rc;
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/*
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* Setup SBI extensions
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* NOTE: This must be the last thing to be initialized.
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*/
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kvm_riscv_vcpu_sbi_init(vcpu);
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/* Reset VCPU */
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kvm_riscv_reset_vcpu(vcpu);
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return 0;
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}
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void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
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{
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/**
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* vcpu with id 0 is the designated boot cpu.
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* Keep all vcpus with non-zero id in power-off state so that
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* they can be brought up using SBI HSM extension.
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*/
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if (vcpu->vcpu_idx != 0)
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kvm_riscv_vcpu_power_off(vcpu);
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}
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void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
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{
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/* Cleanup VCPU AIA context */
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kvm_riscv_vcpu_aia_deinit(vcpu);
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/* Cleanup VCPU timer */
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kvm_riscv_vcpu_timer_deinit(vcpu);
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kvm_riscv_vcpu_pmu_deinit(vcpu);
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/* Free unused pages pre-allocated for G-stage page table mappings */
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kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
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/* Free vector context space for host and guest kernel */
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kvm_riscv_vcpu_free_vector_context(vcpu);
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}
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int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
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{
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return kvm_riscv_vcpu_timer_pending(vcpu);
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}
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void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
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{
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kvm_riscv_aia_wakeon_hgei(vcpu, true);
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}
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void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
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{
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kvm_riscv_aia_wakeon_hgei(vcpu, false);
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}
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int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
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{
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return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) &&
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!vcpu->arch.power_off && !vcpu->arch.pause);
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}
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int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
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}
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bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
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{
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return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false;
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}
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vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
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{
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return VM_FAULT_SIGBUS;
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}
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long kvm_arch_vcpu_async_ioctl(struct file *filp,
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unsigned int ioctl, unsigned long arg)
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{
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struct kvm_vcpu *vcpu = filp->private_data;
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void __user *argp = (void __user *)arg;
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if (ioctl == KVM_INTERRUPT) {
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struct kvm_interrupt irq;
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if (copy_from_user(&irq, argp, sizeof(irq)))
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return -EFAULT;
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if (irq.irq == KVM_INTERRUPT_SET)
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return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT);
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else
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return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
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}
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return -ENOIOCTLCMD;
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}
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long kvm_arch_vcpu_ioctl(struct file *filp,
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unsigned int ioctl, unsigned long arg)
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{
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struct kvm_vcpu *vcpu = filp->private_data;
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void __user *argp = (void __user *)arg;
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long r = -EINVAL;
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switch (ioctl) {
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case KVM_SET_ONE_REG:
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case KVM_GET_ONE_REG: {
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struct kvm_one_reg reg;
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r = -EFAULT;
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if (copy_from_user(®, argp, sizeof(reg)))
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break;
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if (ioctl == KVM_SET_ONE_REG)
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r = kvm_riscv_vcpu_set_reg(vcpu, ®);
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else
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r = kvm_riscv_vcpu_get_reg(vcpu, ®);
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break;
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}
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case KVM_GET_REG_LIST: {
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struct kvm_reg_list __user *user_list = argp;
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struct kvm_reg_list reg_list;
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unsigned int n;
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r = -EFAULT;
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if (copy_from_user(®_list, user_list, sizeof(reg_list)))
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break;
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n = reg_list.n;
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reg_list.n = kvm_riscv_vcpu_num_regs(vcpu);
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if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
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break;
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r = -E2BIG;
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if (n < reg_list.n)
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break;
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r = kvm_riscv_vcpu_copy_reg_indices(vcpu, user_list->reg);
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break;
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}
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default:
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break;
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}
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return r;
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}
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int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
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struct kvm_sregs *sregs)
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{
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return -EINVAL;
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}
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int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
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struct kvm_sregs *sregs)
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{
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return -EINVAL;
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}
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int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
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{
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return -EINVAL;
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}
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int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
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{
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return -EINVAL;
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}
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int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
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struct kvm_translation *tr)
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{
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return -EINVAL;
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}
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int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
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{
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return -EINVAL;
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}
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int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
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{
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return -EINVAL;
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}
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void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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unsigned long mask, val;
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if (READ_ONCE(vcpu->arch.irqs_pending_mask[0])) {
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mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[0], 0);
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val = READ_ONCE(vcpu->arch.irqs_pending[0]) & mask;
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csr->hvip &= ~mask;
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csr->hvip |= val;
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}
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/* Flush AIA high interrupts */
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kvm_riscv_vcpu_aia_flush_interrupts(vcpu);
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}
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void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu)
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{
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unsigned long hvip;
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struct kvm_vcpu_arch *v = &vcpu->arch;
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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/* Read current HVIP and VSIE CSRs */
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csr->vsie = csr_read(CSR_VSIE);
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/* Sync-up HVIP.VSSIP bit changes does by Guest */
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hvip = csr_read(CSR_HVIP);
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if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {
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if (hvip & (1UL << IRQ_VS_SOFT)) {
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if (!test_and_set_bit(IRQ_VS_SOFT,
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v->irqs_pending_mask))
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set_bit(IRQ_VS_SOFT, v->irqs_pending);
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} else {
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if (!test_and_set_bit(IRQ_VS_SOFT,
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v->irqs_pending_mask))
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clear_bit(IRQ_VS_SOFT, v->irqs_pending);
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}
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}
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/* Sync-up AIA high interrupts */
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kvm_riscv_vcpu_aia_sync_interrupts(vcpu);
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/* Sync-up timer CSRs */
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kvm_riscv_vcpu_timer_sync(vcpu);
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}
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int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
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{
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/*
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* We only allow VS-mode software, timer, and external
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* interrupts when irq is one of the local interrupts
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* defined by RISC-V privilege specification.
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*/
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if (irq < IRQ_LOCAL_MAX &&
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irq != IRQ_VS_SOFT &&
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irq != IRQ_VS_TIMER &&
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irq != IRQ_VS_EXT)
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return -EINVAL;
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set_bit(irq, vcpu->arch.irqs_pending);
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smp_mb__before_atomic();
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set_bit(irq, vcpu->arch.irqs_pending_mask);
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kvm_vcpu_kick(vcpu);
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return 0;
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}
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int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
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{
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/*
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* We only allow VS-mode software, timer, and external
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* interrupts when irq is one of the local interrupts
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* defined by RISC-V privilege specification.
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*/
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if (irq < IRQ_LOCAL_MAX &&
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irq != IRQ_VS_SOFT &&
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irq != IRQ_VS_TIMER &&
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irq != IRQ_VS_EXT)
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return -EINVAL;
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clear_bit(irq, vcpu->arch.irqs_pending);
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smp_mb__before_atomic();
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set_bit(irq, vcpu->arch.irqs_pending_mask);
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return 0;
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}
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bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask)
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{
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unsigned long ie;
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ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK)
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<< VSIP_TO_HVIP_SHIFT) & (unsigned long)mask;
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ie |= vcpu->arch.guest_csr.vsie & ~IRQ_LOCAL_MASK &
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(unsigned long)mask;
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if (READ_ONCE(vcpu->arch.irqs_pending[0]) & ie)
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return true;
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/* Check AIA high interrupts */
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return kvm_riscv_vcpu_aia_has_interrupts(vcpu, mask);
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}
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void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.power_off = true;
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kvm_make_request(KVM_REQ_SLEEP, vcpu);
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kvm_vcpu_kick(vcpu);
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}
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void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.power_off = false;
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kvm_vcpu_wake_up(vcpu);
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}
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int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
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struct kvm_mp_state *mp_state)
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{
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if (vcpu->arch.power_off)
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mp_state->mp_state = KVM_MP_STATE_STOPPED;
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else
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mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
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return 0;
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}
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int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
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struct kvm_mp_state *mp_state)
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{
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int ret = 0;
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switch (mp_state->mp_state) {
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case KVM_MP_STATE_RUNNABLE:
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vcpu->arch.power_off = false;
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break;
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case KVM_MP_STATE_STOPPED:
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kvm_riscv_vcpu_power_off(vcpu);
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break;
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default:
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|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
|
|
struct kvm_guest_debug *dbg)
|
|
{
|
|
/* TODO; To be implemented later. */
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
|
|
{
|
|
const unsigned long *isa = vcpu->arch.isa;
|
|
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
|
|
|
|
if (riscv_isa_extension_available(isa, SVPBMT))
|
|
cfg->henvcfg |= ENVCFG_PBMTE;
|
|
|
|
if (riscv_isa_extension_available(isa, SSTC))
|
|
cfg->henvcfg |= ENVCFG_STCE;
|
|
|
|
if (riscv_isa_extension_available(isa, ZICBOM))
|
|
cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
|
|
|
|
if (riscv_isa_extension_available(isa, ZICBOZ))
|
|
cfg->henvcfg |= ENVCFG_CBZE;
|
|
|
|
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
|
|
cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
|
|
if (riscv_isa_extension_available(isa, SSAIA))
|
|
cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC |
|
|
SMSTATEEN0_AIA |
|
|
SMSTATEEN0_AIA_ISEL;
|
|
if (riscv_isa_extension_available(isa, SMSTATEEN))
|
|
cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0;
|
|
}
|
|
}
|
|
|
|
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
|
|
|
|
csr_write(CSR_VSSTATUS, csr->vsstatus);
|
|
csr_write(CSR_VSIE, csr->vsie);
|
|
csr_write(CSR_VSTVEC, csr->vstvec);
|
|
csr_write(CSR_VSSCRATCH, csr->vsscratch);
|
|
csr_write(CSR_VSEPC, csr->vsepc);
|
|
csr_write(CSR_VSCAUSE, csr->vscause);
|
|
csr_write(CSR_VSTVAL, csr->vstval);
|
|
csr_write(CSR_HVIP, csr->hvip);
|
|
csr_write(CSR_VSATP, csr->vsatp);
|
|
csr_write(CSR_HENVCFG, cfg->henvcfg);
|
|
if (IS_ENABLED(CONFIG_32BIT))
|
|
csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);
|
|
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
|
|
csr_write(CSR_HSTATEEN0, cfg->hstateen0);
|
|
if (IS_ENABLED(CONFIG_32BIT))
|
|
csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
|
|
}
|
|
|
|
kvm_riscv_gstage_update_hgatp(vcpu);
|
|
|
|
kvm_riscv_vcpu_timer_restore(vcpu);
|
|
|
|
kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context);
|
|
kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context,
|
|
vcpu->arch.isa);
|
|
kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context);
|
|
kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context,
|
|
vcpu->arch.isa);
|
|
|
|
kvm_riscv_vcpu_aia_load(vcpu, cpu);
|
|
|
|
kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
|
|
|
|
vcpu->cpu = cpu;
|
|
}
|
|
|
|
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
vcpu->cpu = -1;
|
|
|
|
kvm_riscv_vcpu_aia_put(vcpu);
|
|
|
|
kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context,
|
|
vcpu->arch.isa);
|
|
kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
|
|
|
|
kvm_riscv_vcpu_timer_save(vcpu);
|
|
kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context,
|
|
vcpu->arch.isa);
|
|
kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context);
|
|
|
|
csr->vsstatus = csr_read(CSR_VSSTATUS);
|
|
csr->vsie = csr_read(CSR_VSIE);
|
|
csr->vstvec = csr_read(CSR_VSTVEC);
|
|
csr->vsscratch = csr_read(CSR_VSSCRATCH);
|
|
csr->vsepc = csr_read(CSR_VSEPC);
|
|
csr->vscause = csr_read(CSR_VSCAUSE);
|
|
csr->vstval = csr_read(CSR_VSTVAL);
|
|
csr->hvip = csr_read(CSR_HVIP);
|
|
csr->vsatp = csr_read(CSR_VSATP);
|
|
}
|
|
|
|
static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu);
|
|
|
|
if (kvm_request_pending(vcpu)) {
|
|
if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) {
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
rcuwait_wait_event(wait,
|
|
(!vcpu->arch.power_off) && (!vcpu->arch.pause),
|
|
TASK_INTERRUPTIBLE);
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
|
|
if (vcpu->arch.power_off || vcpu->arch.pause) {
|
|
/*
|
|
* Awaken to handle a signal, request to
|
|
* sleep again later.
|
|
*/
|
|
kvm_make_request(KVM_REQ_SLEEP, vcpu);
|
|
}
|
|
}
|
|
|
|
if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
|
|
kvm_riscv_reset_vcpu(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu))
|
|
kvm_riscv_gstage_update_hgatp(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_FENCE_I, vcpu))
|
|
kvm_riscv_fence_i_process(vcpu);
|
|
|
|
/*
|
|
* The generic KVM_REQ_TLB_FLUSH is same as
|
|
* KVM_REQ_HFENCE_GVMA_VMID_ALL
|
|
*/
|
|
if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu))
|
|
kvm_riscv_hfence_gvma_vmid_all_process(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu))
|
|
kvm_riscv_hfence_vvma_all_process(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_HFENCE, vcpu))
|
|
kvm_riscv_hfence_process(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
|
|
kvm_riscv_vcpu_record_steal_time(vcpu);
|
|
}
|
|
}
|
|
|
|
static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
csr_write(CSR_HVIP, csr->hvip);
|
|
kvm_riscv_vcpu_aia_update_hvip(vcpu);
|
|
}
|
|
|
|
static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
|
|
|
|
vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg);
|
|
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
|
|
(cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
|
|
vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0,
|
|
smcsr->sstateen0);
|
|
}
|
|
|
|
static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
|
|
|
|
csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg);
|
|
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
|
|
(cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
|
|
smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0,
|
|
vcpu->arch.host_sstateen0);
|
|
}
|
|
|
|
/*
|
|
* Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
|
|
* the vCPU is running.
|
|
*
|
|
* This must be noinstr as instrumentation may make use of RCU, and this is not
|
|
* safe during the EQS.
|
|
*/
|
|
static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
|
|
{
|
|
kvm_riscv_vcpu_swap_in_guest_state(vcpu);
|
|
guest_state_enter_irqoff();
|
|
__kvm_riscv_switch_to(&vcpu->arch);
|
|
vcpu->arch.last_exit_cpu = vcpu->cpu;
|
|
guest_state_exit_irqoff();
|
|
kvm_riscv_vcpu_swap_in_host_state(vcpu);
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
|
|
{
|
|
int ret;
|
|
struct kvm_cpu_trap trap;
|
|
struct kvm_run *run = vcpu->run;
|
|
|
|
if (!vcpu->arch.ran_atleast_once)
|
|
kvm_riscv_vcpu_setup_config(vcpu);
|
|
|
|
/* Mark this VCPU ran at least once */
|
|
vcpu->arch.ran_atleast_once = true;
|
|
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
|
|
switch (run->exit_reason) {
|
|
case KVM_EXIT_MMIO:
|
|
/* Process MMIO value returned from user-space */
|
|
ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run);
|
|
break;
|
|
case KVM_EXIT_RISCV_SBI:
|
|
/* Process SBI value returned from user-space */
|
|
ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run);
|
|
break;
|
|
case KVM_EXIT_RISCV_CSR:
|
|
/* Process CSR value returned from user-space */
|
|
ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run);
|
|
break;
|
|
default:
|
|
ret = 0;
|
|
break;
|
|
}
|
|
if (ret) {
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
return ret;
|
|
}
|
|
|
|
if (run->immediate_exit) {
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
return -EINTR;
|
|
}
|
|
|
|
vcpu_load(vcpu);
|
|
|
|
kvm_sigset_activate(vcpu);
|
|
|
|
ret = 1;
|
|
run->exit_reason = KVM_EXIT_UNKNOWN;
|
|
while (ret > 0) {
|
|
/* Check conditions before entering the guest */
|
|
ret = xfer_to_guest_mode_handle_work(vcpu);
|
|
if (ret)
|
|
continue;
|
|
ret = 1;
|
|
|
|
kvm_riscv_gstage_vmid_update(vcpu);
|
|
|
|
kvm_riscv_check_vcpu_requests(vcpu);
|
|
|
|
preempt_disable();
|
|
|
|
/* Update AIA HW state before entering guest */
|
|
ret = kvm_riscv_vcpu_aia_update(vcpu);
|
|
if (ret <= 0) {
|
|
preempt_enable();
|
|
continue;
|
|
}
|
|
|
|
local_irq_disable();
|
|
|
|
/*
|
|
* Ensure we set mode to IN_GUEST_MODE after we disable
|
|
* interrupts and before the final VCPU requests check.
|
|
* See the comment in kvm_vcpu_exiting_guest_mode() and
|
|
* Documentation/virt/kvm/vcpu-requests.rst
|
|
*/
|
|
vcpu->mode = IN_GUEST_MODE;
|
|
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
smp_mb__after_srcu_read_unlock();
|
|
|
|
/*
|
|
* We might have got VCPU interrupts updated asynchronously
|
|
* so update it in HW.
|
|
*/
|
|
kvm_riscv_vcpu_flush_interrupts(vcpu);
|
|
|
|
/* Update HVIP CSR for current CPU */
|
|
kvm_riscv_update_hvip(vcpu);
|
|
|
|
if (kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) ||
|
|
kvm_request_pending(vcpu) ||
|
|
xfer_to_guest_mode_work_pending()) {
|
|
vcpu->mode = OUTSIDE_GUEST_MODE;
|
|
local_irq_enable();
|
|
preempt_enable();
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Cleanup stale TLB enteries
|
|
*
|
|
* Note: This should be done after G-stage VMID has been
|
|
* updated using kvm_riscv_gstage_vmid_ver_changed()
|
|
*/
|
|
kvm_riscv_local_tlb_sanitize(vcpu);
|
|
|
|
guest_timing_enter_irqoff();
|
|
|
|
kvm_riscv_vcpu_enter_exit(vcpu);
|
|
|
|
vcpu->mode = OUTSIDE_GUEST_MODE;
|
|
vcpu->stat.exits++;
|
|
|
|
/*
|
|
* Save SCAUSE, STVAL, HTVAL, and HTINST because we might
|
|
* get an interrupt between __kvm_riscv_switch_to() and
|
|
* local_irq_enable() which can potentially change CSRs.
|
|
*/
|
|
trap.sepc = vcpu->arch.guest_context.sepc;
|
|
trap.scause = csr_read(CSR_SCAUSE);
|
|
trap.stval = csr_read(CSR_STVAL);
|
|
trap.htval = csr_read(CSR_HTVAL);
|
|
trap.htinst = csr_read(CSR_HTINST);
|
|
|
|
/* Syncup interrupts state with HW */
|
|
kvm_riscv_vcpu_sync_interrupts(vcpu);
|
|
|
|
/*
|
|
* We must ensure that any pending interrupts are taken before
|
|
* we exit guest timing so that timer ticks are accounted as
|
|
* guest time. Transiently unmask interrupts so that any
|
|
* pending interrupts are taken.
|
|
*
|
|
* There's no barrier which ensures that pending interrupts are
|
|
* recognised, so we just hope that the CPU takes any pending
|
|
* interrupts between the enable and disable.
|
|
*/
|
|
local_irq_enable();
|
|
local_irq_disable();
|
|
|
|
guest_timing_exit_irqoff();
|
|
|
|
local_irq_enable();
|
|
|
|
preempt_enable();
|
|
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
|
|
ret = kvm_riscv_vcpu_exit(vcpu, run, &trap);
|
|
}
|
|
|
|
kvm_sigset_deactivate(vcpu);
|
|
|
|
vcpu_put(vcpu);
|
|
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
|
|
return ret;
|
|
}
|