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563a5255af
Add an implementation of SM3 using the Zvksh extension. The assembly code is derived from OpenSSL code (openssl/openssl#21923) that was dual-licensed so that it could be reused in the kernel. Nevertheless, the assembly has been significantly reworked for integration with the kernel, for example by using a regular .S file instead of the so-called perlasm, using the assembler instead of bare '.inst', and greatly reducing code duplication. Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-developed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Co-developed-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20240122002024.27477-10-ebiggers@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
124 lines
3.9 KiB
ArmAsm
124 lines
3.9 KiB
ArmAsm
/* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
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//
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// This file is dual-licensed, meaning that you can use it under your
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// choice of either of the following two licenses:
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//
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// Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
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//
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// Licensed under the Apache License 2.0 (the "License"). You can obtain
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// a copy in the file LICENSE in the source distribution or at
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// https://www.openssl.org/source/license.html
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//
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// or
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//
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// Copyright (c) 2023, Christoph Müllner <christoph.muellner@vrull.eu>
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// Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
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// Copyright 2024 Google LLC
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The generated code of this file depends on the following RISC-V extensions:
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// - RV64I
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// - RISC-V Vector ('V') with VLEN >= 128
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// - RISC-V Vector SM3 Secure Hash extension ('Zvksh')
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// - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
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#include <linux/cfi_types.h>
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.text
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.option arch, +zvksh, +zvkb
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#define STATEP a0
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#define DATA a1
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#define NUM_BLOCKS a2
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#define STATE v0 // LMUL=2
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#define PREV_STATE v2 // LMUL=2
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#define W0 v4 // LMUL=2
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#define W1 v6 // LMUL=2
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#define VTMP v8 // LMUL=2
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.macro sm3_8rounds i, w0, w1
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// Do 4 rounds using W_{0+i}..W_{7+i}.
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vsm3c.vi STATE, \w0, \i + 0
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vslidedown.vi VTMP, \w0, 2
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vsm3c.vi STATE, VTMP, \i + 1
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// Compute W_{4+i}..W_{11+i}.
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vslidedown.vi VTMP, \w0, 4
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vslideup.vi VTMP, \w1, 4
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// Do 4 rounds using W_{4+i}..W_{11+i}.
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vsm3c.vi STATE, VTMP, \i + 2
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vslidedown.vi VTMP, VTMP, 2
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vsm3c.vi STATE, VTMP, \i + 3
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.if \i < 28
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// Compute W_{16+i}..W_{23+i}.
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vsm3me.vv \w0, \w1, \w0
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.endif
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// For the next 8 rounds, w0 and w1 are swapped.
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.endm
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// void sm3_transform_zvksh_zvkb(u32 state[8], const u8 *data, int num_blocks);
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SYM_TYPED_FUNC_START(sm3_transform_zvksh_zvkb)
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// Load the state and endian-swap each 32-bit word.
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vsetivli zero, 8, e32, m2, ta, ma
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vle32.v STATE, (STATEP)
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vrev8.v STATE, STATE
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.Lnext_block:
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addi NUM_BLOCKS, NUM_BLOCKS, -1
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// Save the previous state, as it's needed later.
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vmv.v.v PREV_STATE, STATE
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// Load the next 512-bit message block into W0-W1.
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vle32.v W0, (DATA)
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addi DATA, DATA, 32
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vle32.v W1, (DATA)
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addi DATA, DATA, 32
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// Do the 64 rounds of SM3.
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sm3_8rounds 0, W0, W1
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sm3_8rounds 4, W1, W0
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sm3_8rounds 8, W0, W1
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sm3_8rounds 12, W1, W0
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sm3_8rounds 16, W0, W1
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sm3_8rounds 20, W1, W0
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sm3_8rounds 24, W0, W1
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sm3_8rounds 28, W1, W0
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// XOR in the previous state.
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vxor.vv STATE, STATE, PREV_STATE
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// Repeat if more blocks remain.
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bnez NUM_BLOCKS, .Lnext_block
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// Store the new state and return.
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vrev8.v STATE, STATE
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vse32.v STATE, (STATEP)
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ret
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SYM_FUNC_END(sm3_transform_zvksh_zvkb)
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