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This adds support for hardware-assisted userspace irq masking for special priority levels. Due to the SR.IMASK interactivity, only some platforms implement this in hardware (including but not limited to SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU needs to wire this up on its own, for now only SH7786 is wired up as an example. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
14 lines
467 B
Plaintext
14 lines
467 B
Plaintext
config INTC_USERIMASK
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bool "Userspace interrupt masking support"
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depends on ARCH_SHMOBILE || (SUPERH && CPU_SH4A)
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help
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This enables support for hardware-assisted userspace hardirq
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masking.
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SH-4A and newer interrupt blocks all support a special shadowed
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page with all non-masking registers obscured when mapped in to
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userspace. This is primarily for use by userspace device
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drivers that are using special priority levels.
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If in doubt, say N.
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