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6bb27d7349
Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
192 lines
4.6 KiB
C
192 lines
4.6 KiB
C
/* linux/arch/arm/mach-pxa/xcep.c
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*
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* Support for the Iskratel Electronics XCEP platform as used in
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* the Libera instruments from Instrumentation Technologies.
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*
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* Author: Ales Bardorfer <ales@i-tech.si>
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* Contributions by: Abbott, MG (Michael) <michael.abbott@diamond.ac.uk>
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* Contributions by: Matej Kenda <matej.kenda@i-tech.si>
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* Created: June 2006
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* Copyright: (C) 2006-2009 Instrumentation Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c/pxa-i2c.h>
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#include <linux/smc91x.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/pxa25x.h>
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#include <mach/smemc.h>
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#include "generic.h"
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#define XCEP_ETH_PHYS (PXA_CS3_PHYS + 0x00000300)
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#define XCEP_ETH_PHYS_END (PXA_CS3_PHYS + 0x000fffff)
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#define XCEP_ETH_ATTR (PXA_CS3_PHYS + 0x02000000)
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#define XCEP_ETH_ATTR_END (PXA_CS3_PHYS + 0x020fffff)
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#define XCEP_ETH_IRQ IRQ_GPIO0
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/* XCEP CPLD base */
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#define XCEP_CPLD_BASE 0xf0000000
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/* Flash partitions. */
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static struct mtd_partition xcep_partitions[] = {
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{
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.name = "Bootloader",
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.size = 0x00040000,
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.offset = 0,
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.mask_flags = MTD_WRITEABLE
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}, {
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.name = "Bootloader ENV",
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.size = 0x00040000,
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.offset = 0x00040000,
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.mask_flags = MTD_WRITEABLE
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}, {
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.name = "Kernel",
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.size = 0x00100000,
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.offset = 0x00080000,
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}, {
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.name = "Rescue fs",
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.size = 0x00280000,
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.offset = 0x00180000,
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}, {
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.name = "Filesystem",
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.size = MTDPART_SIZ_FULL,
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.offset = 0x00400000
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}
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};
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static struct physmap_flash_data xcep_flash_data[] = {
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{
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.width = 4, /* bankwidth in bytes */
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.parts = xcep_partitions,
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.nr_parts = ARRAY_SIZE(xcep_partitions)
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}
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};
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static struct resource flash_resource = {
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.start = PXA_CS0_PHYS,
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.end = PXA_CS0_PHYS + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = xcep_flash_data,
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},
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.resource = &flash_resource,
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.num_resources = 1,
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};
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/* SMC LAN91C111 network controller. */
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static struct resource smc91x_resources[] = {
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[0] = {
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.name = "smc91x-regs",
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.start = XCEP_ETH_PHYS,
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.end = XCEP_ETH_PHYS_END,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = XCEP_ETH_IRQ,
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.end = XCEP_ETH_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.name = "smc91x-attrib",
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.start = XCEP_ETH_ATTR,
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.end = XCEP_ETH_ATTR_END,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct smc91x_platdata xcep_smc91x_info = {
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.flags = SMC91X_USE_32BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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.dev = {
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.platform_data = &xcep_smc91x_info,
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},
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};
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static struct platform_device *devices[] __initdata = {
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&flash_device,
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&smc91x_device,
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};
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/* We have to state that there are HWMON devices on the I2C bus on XCEP.
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* Drivers for HWMON verify capabilities of the adapter when loading and
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* refuse to attach if the adapter doesn't support HWMON class of devices. */
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static struct i2c_pxa_platform_data xcep_i2c_platform_data = {
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.class = I2C_CLASS_HWMON
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};
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static mfp_cfg_t xcep_pin_config[] __initdata = {
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GPIO79_nCS_3, /* SMC 91C111 chip select. */
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GPIO80_nCS_4, /* CPLD chip select. */
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/* SSP communication to MSP430 */
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GPIO23_SSP1_SCLK,
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GPIO24_SSP1_SFRM,
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GPIO25_SSP1_TXD,
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GPIO26_SSP1_RXD,
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GPIO27_SSP1_EXTCLK
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};
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static void __init xcep_init(void)
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{
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pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config));
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pxa_set_ffuart_info(NULL);
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pxa_set_btuart_info(NULL);
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pxa_set_stuart_info(NULL);
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pxa_set_hwuart_info(NULL);
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/* See Intel XScale Developer's Guide for details */
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/* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
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__raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
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/* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */
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__raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2);
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platform_add_devices(ARRAY_AND_SIZE(devices));
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pxa_set_i2c_info(&xcep_i2c_platform_data);
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}
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MACHINE_START(XCEP, "Iskratel XCEP")
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.atag_offset = 0x100,
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.init_machine = xcep_init,
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.map_io = pxa25x_map_io,
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.nr_irqs = PXA_NR_IRQS,
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.init_irq = pxa25x_init_irq,
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.handle_irq = pxa25x_handle_irq,
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.init_time = pxa_timer_init,
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.restart = pxa_restart,
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MACHINE_END
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