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ce7f93680a
Improve the firmware selection by adding 2 cases where we should use the optimized firmware: * when the actual PCIe link width is lower than 8x. * when the board is plugged to one of the new Intel PCIe chipsets that are known to provide aligned PCIe completions. The patch actually raises two concerns: * We might want to add a generic PCI function to get the PCIe link width since some other drivers (at least ipath) do the same. But we probably do not want to add a new function for every PCIe capability. I will probably look at it and discuss it on linux-pci in the future. * As requested during the submission, the PCI ids of chipsets that are known to provided aligned completion are defined in the myri10ge code. If we keep adding new ones, it might become better to move them to pciids.h. But, this sort of quirk to detect these chipsets are very specific to our NIC, I don't think it is worth moving it to the PCI core until somebody else really needs it. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Jeff Garzik <jeff@garzik.org> |
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| Makefile | ||
| myri10ge_mcp_gen_header.h | ||
| myri10ge_mcp.h | ||
| myri10ge.c | ||