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54293ec307
Here we define the addresses and bit-fields of the Configuration and
Status Registers (CSRs) for some of the hardware functional units on
the OCTEON SOC.
Definitions are needed for:
CIU -- Central Interrupt Unit.
GPIO -- General Purpose Input Output.
IOB -- Input / Output {Busing,Bridge}.
IPD -- Input Packet Data unit.
L2C -- Level-2 Cache controller.
L2D -- Level-2 Data cache.
L2T -- Level-2 cache Tag.
LED -- Light Emitting Diode controller.
MIO -- Miscellaneous Input / Output.
POW -- Packet Order / Work unit.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
220 lines
6.2 KiB
C
220 lines
6.2 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_GPIO_DEFS_H__
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#define __CVMX_GPIO_DEFS_H__
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#define CVMX_GPIO_BIT_CFGX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
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#define CVMX_GPIO_BOOT_ENA \
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CVMX_ADD_IO_SEG(0x00010700000008A8ull)
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#define CVMX_GPIO_CLK_GENX(offset) \
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CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
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#define CVMX_GPIO_DBG_ENA \
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CVMX_ADD_IO_SEG(0x00010700000008A0ull)
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#define CVMX_GPIO_INT_CLR \
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CVMX_ADD_IO_SEG(0x0001070000000898ull)
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#define CVMX_GPIO_RX_DAT \
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CVMX_ADD_IO_SEG(0x0001070000000880ull)
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#define CVMX_GPIO_TX_CLR \
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CVMX_ADD_IO_SEG(0x0001070000000890ull)
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#define CVMX_GPIO_TX_SET \
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CVMX_ADD_IO_SEG(0x0001070000000888ull)
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#define CVMX_GPIO_XBIT_CFGX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
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union cvmx_gpio_bit_cfgx {
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uint64_t u64;
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struct cvmx_gpio_bit_cfgx_s {
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uint64_t reserved_15_63:49;
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uint64_t clk_gen:1;
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uint64_t clk_sel:2;
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uint64_t fil_sel:4;
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uint64_t fil_cnt:4;
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uint64_t int_type:1;
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uint64_t int_en:1;
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uint64_t rx_xor:1;
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uint64_t tx_oe:1;
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} s;
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struct cvmx_gpio_bit_cfgx_cn30xx {
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uint64_t reserved_12_63:52;
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uint64_t fil_sel:4;
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uint64_t fil_cnt:4;
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uint64_t int_type:1;
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uint64_t int_en:1;
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uint64_t rx_xor:1;
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uint64_t tx_oe:1;
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} cn30xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
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struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
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struct cvmx_gpio_bit_cfgx_s cn52xx;
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struct cvmx_gpio_bit_cfgx_s cn52xxp1;
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struct cvmx_gpio_bit_cfgx_s cn56xx;
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struct cvmx_gpio_bit_cfgx_s cn56xxp1;
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struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
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};
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union cvmx_gpio_boot_ena {
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uint64_t u64;
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struct cvmx_gpio_boot_ena_s {
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uint64_t reserved_12_63:52;
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uint64_t boot_ena:4;
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uint64_t reserved_0_7:8;
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} s;
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struct cvmx_gpio_boot_ena_s cn30xx;
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struct cvmx_gpio_boot_ena_s cn31xx;
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struct cvmx_gpio_boot_ena_s cn50xx;
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};
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union cvmx_gpio_clk_genx {
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uint64_t u64;
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struct cvmx_gpio_clk_genx_s {
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uint64_t reserved_32_63:32;
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uint64_t n:32;
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} s;
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struct cvmx_gpio_clk_genx_s cn52xx;
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struct cvmx_gpio_clk_genx_s cn52xxp1;
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struct cvmx_gpio_clk_genx_s cn56xx;
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struct cvmx_gpio_clk_genx_s cn56xxp1;
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};
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union cvmx_gpio_dbg_ena {
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uint64_t u64;
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struct cvmx_gpio_dbg_ena_s {
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uint64_t reserved_21_63:43;
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uint64_t dbg_ena:21;
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} s;
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struct cvmx_gpio_dbg_ena_s cn30xx;
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struct cvmx_gpio_dbg_ena_s cn31xx;
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struct cvmx_gpio_dbg_ena_s cn50xx;
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};
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union cvmx_gpio_int_clr {
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uint64_t u64;
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struct cvmx_gpio_int_clr_s {
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uint64_t reserved_16_63:48;
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uint64_t type:16;
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} s;
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struct cvmx_gpio_int_clr_s cn30xx;
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struct cvmx_gpio_int_clr_s cn31xx;
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struct cvmx_gpio_int_clr_s cn38xx;
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struct cvmx_gpio_int_clr_s cn38xxp2;
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struct cvmx_gpio_int_clr_s cn50xx;
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struct cvmx_gpio_int_clr_s cn52xx;
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struct cvmx_gpio_int_clr_s cn52xxp1;
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struct cvmx_gpio_int_clr_s cn56xx;
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struct cvmx_gpio_int_clr_s cn56xxp1;
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struct cvmx_gpio_int_clr_s cn58xx;
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struct cvmx_gpio_int_clr_s cn58xxp1;
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};
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union cvmx_gpio_rx_dat {
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uint64_t u64;
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struct cvmx_gpio_rx_dat_s {
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uint64_t reserved_24_63:40;
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uint64_t dat:24;
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} s;
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struct cvmx_gpio_rx_dat_s cn30xx;
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struct cvmx_gpio_rx_dat_s cn31xx;
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struct cvmx_gpio_rx_dat_cn38xx {
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uint64_t reserved_16_63:48;
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uint64_t dat:16;
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} cn38xx;
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struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
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struct cvmx_gpio_rx_dat_s cn50xx;
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struct cvmx_gpio_rx_dat_cn38xx cn52xx;
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struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
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struct cvmx_gpio_rx_dat_cn38xx cn56xx;
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struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
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struct cvmx_gpio_rx_dat_cn38xx cn58xx;
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struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
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};
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union cvmx_gpio_tx_clr {
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uint64_t u64;
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struct cvmx_gpio_tx_clr_s {
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uint64_t reserved_24_63:40;
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uint64_t clr:24;
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} s;
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struct cvmx_gpio_tx_clr_s cn30xx;
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struct cvmx_gpio_tx_clr_s cn31xx;
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struct cvmx_gpio_tx_clr_cn38xx {
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uint64_t reserved_16_63:48;
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uint64_t clr:16;
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} cn38xx;
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struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
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struct cvmx_gpio_tx_clr_s cn50xx;
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struct cvmx_gpio_tx_clr_cn38xx cn52xx;
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struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
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struct cvmx_gpio_tx_clr_cn38xx cn56xx;
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struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
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struct cvmx_gpio_tx_clr_cn38xx cn58xx;
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struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
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};
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union cvmx_gpio_tx_set {
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uint64_t u64;
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struct cvmx_gpio_tx_set_s {
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uint64_t reserved_24_63:40;
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uint64_t set:24;
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} s;
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struct cvmx_gpio_tx_set_s cn30xx;
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struct cvmx_gpio_tx_set_s cn31xx;
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struct cvmx_gpio_tx_set_cn38xx {
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uint64_t reserved_16_63:48;
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uint64_t set:16;
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} cn38xx;
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struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
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struct cvmx_gpio_tx_set_s cn50xx;
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struct cvmx_gpio_tx_set_cn38xx cn52xx;
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struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
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struct cvmx_gpio_tx_set_cn38xx cn56xx;
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struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
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struct cvmx_gpio_tx_set_cn38xx cn58xx;
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struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
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};
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union cvmx_gpio_xbit_cfgx {
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uint64_t u64;
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struct cvmx_gpio_xbit_cfgx_s {
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uint64_t reserved_12_63:52;
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uint64_t fil_sel:4;
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uint64_t fil_cnt:4;
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uint64_t reserved_2_3:2;
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uint64_t rx_xor:1;
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uint64_t tx_oe:1;
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} s;
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struct cvmx_gpio_xbit_cfgx_s cn30xx;
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struct cvmx_gpio_xbit_cfgx_s cn31xx;
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struct cvmx_gpio_xbit_cfgx_s cn50xx;
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};
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#endif
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