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42d5ec9547
Adding timeout for maximum allowed time for FPGA to go to operating mode after a FPGA region has been programmed. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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altera-fpga2sdram.c | ||
altera-freeze-bridge.c | ||
altera-hps2fpga.c | ||
fpga-bridge.c | ||
fpga-mgr.c | ||
fpga-region.c | ||
ice40-spi.c | ||
Kconfig | ||
Makefile | ||
socfpga-a10.c | ||
socfpga.c | ||
ts73xx-fpga.c | ||
xilinx-spi.c | ||
zynq-fpga.c |