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7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
68 lines
1.6 KiB
C
68 lines
1.6 KiB
C
/*
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* include/asm-mips/txx9tmr.h
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* TX39/TX49 timer controller definitions.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_TXX9TMR_H
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#define __ASM_TXX9TMR_H
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#include <linux/types.h>
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struct txx9_tmr_reg {
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u32 tcr;
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u32 tisr;
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u32 cpra;
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u32 cprb;
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u32 itmr;
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u32 unused0[3];
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u32 ccdr;
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u32 unused1[3];
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u32 pgmr;
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u32 unused2[3];
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u32 wtmr;
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u32 unused3[43];
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u32 trr;
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};
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/* TMTCR : Timer Control */
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#define TXx9_TMTCR_TCE 0x00000080
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#define TXx9_TMTCR_CCDE 0x00000040
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#define TXx9_TMTCR_CRE 0x00000020
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#define TXx9_TMTCR_ECES 0x00000008
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#define TXx9_TMTCR_CCS 0x00000004
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#define TXx9_TMTCR_TMODE_MASK 0x00000003
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#define TXx9_TMTCR_TMODE_ITVL 0x00000000
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#define TXx9_TMTCR_TMODE_PGEN 0x00000001
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#define TXx9_TMTCR_TMODE_WDOG 0x00000002
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/* TMTISR : Timer Int. Status */
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#define TXx9_TMTISR_TPIBS 0x00000004
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#define TXx9_TMTISR_TPIAS 0x00000002
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#define TXx9_TMTISR_TIIS 0x00000001
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/* TMITMR : Interval Timer Mode */
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#define TXx9_TMITMR_TIIE 0x00008000
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#define TXx9_TMITMR_TZCE 0x00000001
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/* TMWTMR : Watchdog Timer Mode */
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#define TXx9_TMWTMR_TWIE 0x00008000
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#define TXx9_TMWTMR_WDIS 0x00000080
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#define TXx9_TMWTMR_TWC 0x00000001
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void txx9_clocksource_init(unsigned long baseaddr,
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unsigned int imbusclk);
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void txx9_clockevent_init(unsigned long baseaddr, int irq,
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unsigned int imbusclk);
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void txx9_tmr_init(unsigned long baseaddr);
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#ifdef CONFIG_CPU_TX39XX
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#define TXX9_TIMER_BITS 24
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#else
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#define TXX9_TIMER_BITS 32
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#endif
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#endif /* __ASM_TXX9TMR_H */
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