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a924eae751
Typcasting "irq_state" leads to the below static checker warning:
The fix is to declare "irq_state" as unsigned long instead of u32.
drivers/gpio/gpio-sifive.c:97 sifive_gpio_irq_enable()
warn: passing casted pointer '&chip->irq_state' to
'assign_bit()' 32 vs 64.
Fixes: 96868dce64
("gpio/sifive: Add GPIO driver for SiFive SoCs")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Link: https://lore.kernel.org/r/1580189061-14091-1-git-send-email-yash.shah@sifive.com
Reviewed-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
253 lines
7.1 KiB
C
253 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 SiFive
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/of_irq.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#define SIFIVE_GPIO_INPUT_VAL 0x00
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#define SIFIVE_GPIO_INPUT_EN 0x04
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#define SIFIVE_GPIO_OUTPUT_EN 0x08
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#define SIFIVE_GPIO_OUTPUT_VAL 0x0C
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#define SIFIVE_GPIO_RISE_IE 0x18
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#define SIFIVE_GPIO_RISE_IP 0x1C
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#define SIFIVE_GPIO_FALL_IE 0x20
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#define SIFIVE_GPIO_FALL_IP 0x24
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#define SIFIVE_GPIO_HIGH_IE 0x28
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#define SIFIVE_GPIO_HIGH_IP 0x2C
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#define SIFIVE_GPIO_LOW_IE 0x30
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#define SIFIVE_GPIO_LOW_IP 0x34
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#define SIFIVE_GPIO_OUTPUT_XOR 0x40
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#define SIFIVE_GPIO_MAX 32
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#define SIFIVE_GPIO_IRQ_OFFSET 7
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struct sifive_gpio {
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void __iomem *base;
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struct gpio_chip gc;
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struct regmap *regs;
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unsigned long irq_state;
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unsigned int trigger[SIFIVE_GPIO_MAX];
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unsigned int irq_parent[SIFIVE_GPIO_MAX];
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};
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static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
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{
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unsigned long flags;
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unsigned int trigger;
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spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
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trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
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regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
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(trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
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regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),
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(trigger & IRQ_TYPE_EDGE_FALLING) ? BIT(offset) : 0);
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regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),
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(trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
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regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
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(trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
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spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
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}
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static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d);
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if (offset < 0 || offset >= gc->ngpio)
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return -EINVAL;
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chip->trigger[offset] = trigger;
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sifive_gpio_set_ie(chip, offset);
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return 0;
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}
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static void sifive_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
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u32 bit = BIT(offset);
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unsigned long flags;
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irq_chip_enable_parent(d);
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/* Switch to input */
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gc->direction_input(gc, offset);
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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/* Clear any sticky pending interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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/* Enable interrupts */
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assign_bit(offset, &chip->irq_state, 1);
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sifive_gpio_set_ie(chip, offset);
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}
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static void sifive_gpio_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
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assign_bit(offset, &chip->irq_state, 0);
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sifive_gpio_set_ie(chip, offset);
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irq_chip_disable_parent(d);
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}
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static void sifive_gpio_irq_eoi(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
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u32 bit = BIT(offset);
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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/* Clear all pending interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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irq_chip_eoi_parent(d);
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}
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static struct irq_chip sifive_gpio_irqchip = {
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.name = "sifive-gpio",
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.irq_set_type = sifive_gpio_irq_set_type,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_enable = sifive_gpio_irq_enable,
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.irq_disable = sifive_gpio_irq_disable,
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.irq_eoi = sifive_gpio_irq_eoi,
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};
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static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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*parent_type = IRQ_TYPE_NONE;
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*parent = child + SIFIVE_GPIO_IRQ_OFFSET;
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return 0;
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}
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static const struct regmap_config sifive_gpio_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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.disable_locking = true,
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};
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static int sifive_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct device_node *irq_parent;
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struct irq_domain *parent;
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struct gpio_irq_chip *girq;
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struct sifive_gpio *chip;
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int ret, ngpio;
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(chip->base)) {
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dev_err(dev, "failed to allocate device memory\n");
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return PTR_ERR(chip->base);
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}
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chip->regs = devm_regmap_init_mmio(dev, chip->base,
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&sifive_gpio_regmap_config);
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if (IS_ERR(chip->regs))
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return PTR_ERR(chip->regs);
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ngpio = of_irq_count(node);
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if (ngpio >= SIFIVE_GPIO_MAX) {
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dev_err(dev, "Too many GPIO interrupts (max=%d)\n",
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SIFIVE_GPIO_MAX);
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return -ENXIO;
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}
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irq_parent = of_irq_find_parent(node);
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if (!irq_parent) {
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dev_err(dev, "no IRQ parent node\n");
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return -ENODEV;
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}
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parent = irq_find_host(irq_parent);
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if (!parent) {
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dev_err(dev, "no IRQ parent domain\n");
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return -ENODEV;
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}
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ret = bgpio_init(&chip->gc, dev, 4,
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chip->base + SIFIVE_GPIO_INPUT_VAL,
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chip->base + SIFIVE_GPIO_OUTPUT_VAL,
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NULL,
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chip->base + SIFIVE_GPIO_OUTPUT_EN,
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chip->base + SIFIVE_GPIO_INPUT_EN,
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0);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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}
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/* Disable all GPIO interrupts before enabling parent interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
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chip->irq_state = 0;
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chip->gc.base = -1;
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chip->gc.ngpio = ngpio;
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chip->gc.label = dev_name(dev);
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chip->gc.parent = dev;
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chip->gc.owner = THIS_MODULE;
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girq = &chip->gc.irq;
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girq->chip = &sifive_gpio_irqchip;
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girq->fwnode = of_node_to_fwnode(node);
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girq->parent_domain = parent;
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girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
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girq->handler = handle_bad_irq;
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girq->default_type = IRQ_TYPE_NONE;
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platform_set_drvdata(pdev, chip);
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return gpiochip_add_data(&chip->gc, chip);
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}
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static const struct of_device_id sifive_gpio_match[] = {
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{ .compatible = "sifive,gpio0" },
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{ .compatible = "sifive,fu540-c000-gpio" },
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{ },
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};
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static struct platform_driver sifive_gpio_driver = {
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.probe = sifive_gpio_probe,
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.driver = {
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.name = "sifive_gpio",
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.of_match_table = of_match_ptr(sifive_gpio_match),
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},
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};
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builtin_platform_driver(sifive_gpio_driver)
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