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The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)). It further advises that if a board has this pin strapped in mode 1 and mode 2, then to ensure proper operation of the PHY, a software workaround must be implemented. Since it is not possible to detect in software if RX_DV/RX_CTRL pin is incorrectly strapped, add a device-tree property for the board to advertise this and allow corrective action in software. [1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> [nsekhar@ti.com: rebase to mainline, split documentation into separate patch] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| mediatek,mt7620-gsw.txt | ||
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| phy.txt | ||
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| ralink,rt2880-net.txt | ||
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| rockchip-dwmac.txt | ||
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| snps,dwc-qos-ethernet.txt | ||
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| ti,dp83867.txt | ||
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| xilinx_gmii2rgmii.txt | ||