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As stated in the documentation and implied by its name, the ppo
(preserved program order) relation is intended to link po-earlier
to po-later instructions under certain conditions. However, a
corner case currently allows instructions to be linked by ppo that
are not executed by the same thread, i.e., instructions are being
linked that have no po relation.
This happens due to the mb/strong-fence/fence relations, which (as
one case) provide order when locks are passed between threads
followed by an smp_mb__after_unlock_lock() fence. This is
illustrated in the following litmus test (as can be seen when using
herd7 with `doshow ppo`):
P0(spinlock_t *x, spinlock_t *y)
{
spin_lock(x);
spin_unlock(x);
}
P1(spinlock_t *x, spinlock_t *y)
{
spin_lock(x);
smp_mb__after_unlock_lock();
*y = 1;
}
The ppo relation will link P0's spin_lock(x) and P1's *y=1, because
P0 passes a lock to P1 which then uses this fence.
The patch makes ppo a subrelation of po by letting fence contribute
to ppo only in case the fence links events of the same thread.
Signed-off-by: Jonas Oberhauser <jonas.oberhauser@huaweicloud.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
217 lines
7.8 KiB
Plaintext
217 lines
7.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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(*
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* Copyright (C) 2015 Jade Alglave <j.alglave@ucl.ac.uk>,
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* Copyright (C) 2016 Luc Maranget <luc.maranget@inria.fr> for Inria
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* Copyright (C) 2017 Alan Stern <stern@rowland.harvard.edu>,
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* Andrea Parri <parri.andrea@gmail.com>
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*
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* An earlier version of this file appeared in the companion webpage for
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* "Frightening small children and disconcerting grown-ups: Concurrency
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* in the Linux kernel" by Alglave, Maranget, McKenney, Parri, and Stern,
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* which appeared in ASPLOS 2018.
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*)
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"Linux-kernel memory consistency model"
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(*
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* File "lock.cat" handles locks and is experimental.
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* It can be replaced by include "cos.cat" for tests that do not use locks.
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*)
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include "lock.cat"
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(*******************)
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(* Basic relations *)
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(*******************)
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(* Release Acquire *)
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let acq-po = [Acquire] ; po ; [M]
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let po-rel = [M] ; po ; [Release]
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let po-unlock-lock-po = po ; [UL] ; (po|rf) ; [LKR] ; po
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(* Fences *)
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let R4rmb = R \ Noreturn (* Reads for which rmb works *)
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let rmb = [R4rmb] ; fencerel(Rmb) ; [R4rmb]
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let wmb = [W] ; fencerel(Wmb) ; [W]
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let mb = ([M] ; fencerel(Mb) ; [M]) |
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([M] ; fencerel(Before-atomic) ; [RMW] ; po? ; [M]) |
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([M] ; po? ; [RMW] ; fencerel(After-atomic) ; [M]) |
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([M] ; po? ; [LKW] ; fencerel(After-spinlock) ; [M]) |
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(*
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* Note: The po-unlock-lock-po relation only passes the lock to the direct
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* successor, perhaps giving the impression that the ordering of the
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* smp_mb__after_unlock_lock() fence only affects a single lock handover.
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* However, in a longer sequence of lock handovers, the implicit
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* A-cumulative release fences of lock-release ensure that any stores that
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* propagate to one of the involved CPUs before it hands over the lock to
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* the next CPU will also propagate to the final CPU handing over the lock
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* to the CPU that executes the fence. Therefore, all those stores are
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* also affected by the fence.
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*)
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([M] ; po-unlock-lock-po ;
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[After-unlock-lock] ; po ; [M]) |
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([M] ; po? ; [Srcu-unlock] ; fencerel(After-srcu-read-unlock) ; [M])
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let gp = po ; [Sync-rcu | Sync-srcu] ; po?
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let strong-fence = mb | gp
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let nonrw-fence = strong-fence | po-rel | acq-po
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let fence = nonrw-fence | wmb | rmb
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let barrier = fencerel(Barrier | Rmb | Wmb | Mb | Sync-rcu | Sync-srcu |
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Before-atomic | After-atomic | Acquire | Release |
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Rcu-lock | Rcu-unlock | Srcu-lock | Srcu-unlock) |
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(po ; [Release]) | ([Acquire] ; po)
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(**********************************)
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(* Fundamental coherence ordering *)
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(**********************************)
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(* Sequential Consistency Per Variable *)
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let com = rf | co | fr
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acyclic po-loc | com as coherence
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(* Atomic Read-Modify-Write *)
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empty rmw & (fre ; coe) as atomic
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(**********************************)
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(* Instruction execution ordering *)
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(**********************************)
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(* Preserved Program Order *)
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let dep = addr | data
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let rwdep = (dep | ctrl) ; [W]
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let overwrite = co | fr
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let to-w = rwdep | (overwrite & int) | (addr ; [Plain] ; wmb)
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let to-r = (addr ; [R]) | (dep ; [Marked] ; rfi)
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let ppo = to-r | to-w | (fence & int) | (po-unlock-lock-po & int)
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(* Propagation: Ordering from release operations and strong fences. *)
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let A-cumul(r) = (rfe ; [Marked])? ; r
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let rmw-sequence = (rf ; rmw)*
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let cumul-fence = [Marked] ; (A-cumul(strong-fence | po-rel) | wmb |
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po-unlock-lock-po) ; [Marked] ; rmw-sequence
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let prop = [Marked] ; (overwrite & ext)? ; cumul-fence* ;
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[Marked] ; rfe? ; [Marked]
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(*
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* Happens Before: Ordering from the passage of time.
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* No fences needed here for prop because relation confined to one process.
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*)
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let hb = [Marked] ; (ppo | rfe | ((prop \ id) & int)) ; [Marked]
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acyclic hb as happens-before
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(****************************************)
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(* Write and fence propagation ordering *)
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(****************************************)
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(* Propagation: Each non-rf link needs a strong fence. *)
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let pb = prop ; strong-fence ; hb* ; [Marked]
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acyclic pb as propagation
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(*******)
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(* RCU *)
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(*******)
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(*
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* Effects of read-side critical sections proceed from the rcu_read_unlock()
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* or srcu_read_unlock() backwards on the one hand, and from the
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* rcu_read_lock() or srcu_read_lock() forwards on the other hand.
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*
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* In the definition of rcu-fence below, the po term at the left-hand side
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* of each disjunct and the po? term at the right-hand end have been factored
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* out. They have been moved into the definitions of rcu-link and rb.
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* This was necessary in order to apply the "& loc" tests correctly.
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*)
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let rcu-gp = [Sync-rcu] (* Compare with gp *)
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let srcu-gp = [Sync-srcu]
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let rcu-rscsi = rcu-rscs^-1
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let srcu-rscsi = srcu-rscs^-1
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(*
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* The synchronize_rcu() strong fence is special in that it can order not
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* one but two non-rf relations, but only in conjunction with an RCU
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* read-side critical section.
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*)
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let rcu-link = po? ; hb* ; pb* ; prop ; po
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(*
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* Any sequence containing at least as many grace periods as RCU read-side
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* critical sections (joined by rcu-link) induces order like a generalized
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* inter-CPU strong fence.
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* Likewise for SRCU grace periods and read-side critical sections, provided
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* the synchronize_srcu() and srcu_read_[un]lock() calls refer to the same
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* struct srcu_struct location.
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*)
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let rec rcu-order = rcu-gp | srcu-gp |
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(rcu-gp ; rcu-link ; rcu-rscsi) |
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((srcu-gp ; rcu-link ; srcu-rscsi) & loc) |
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(rcu-rscsi ; rcu-link ; rcu-gp) |
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((srcu-rscsi ; rcu-link ; srcu-gp) & loc) |
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(rcu-gp ; rcu-link ; rcu-order ; rcu-link ; rcu-rscsi) |
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((srcu-gp ; rcu-link ; rcu-order ; rcu-link ; srcu-rscsi) & loc) |
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(rcu-rscsi ; rcu-link ; rcu-order ; rcu-link ; rcu-gp) |
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((srcu-rscsi ; rcu-link ; rcu-order ; rcu-link ; srcu-gp) & loc) |
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(rcu-order ; rcu-link ; rcu-order)
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let rcu-fence = po ; rcu-order ; po?
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let fence = fence | rcu-fence
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let strong-fence = strong-fence | rcu-fence
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(* rb orders instructions just as pb does *)
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let rb = prop ; rcu-fence ; hb* ; pb* ; [Marked]
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irreflexive rb as rcu
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(*
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* The happens-before, propagation, and rcu constraints are all
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* expressions of temporal ordering. They could be replaced by
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* a single constraint on an "executes-before" relation, xb:
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*
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* let xb = hb | pb | rb
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* acyclic xb as executes-before
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*)
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(*********************************)
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(* Plain accesses and data races *)
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(*********************************)
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(* Warn about plain writes and marked accesses in the same region *)
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let mixed-accesses = ([Plain & W] ; (po-loc \ barrier) ; [Marked]) |
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([Marked] ; (po-loc \ barrier) ; [Plain & W])
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flag ~empty mixed-accesses as mixed-accesses
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(* Executes-before and visibility *)
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let xbstar = (hb | pb | rb)*
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let vis = cumul-fence* ; rfe? ; [Marked] ;
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((strong-fence ; [Marked] ; xbstar) | (xbstar & int))
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(* Boundaries for lifetimes of plain accesses *)
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let w-pre-bounded = [Marked] ; (addr | fence)?
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let r-pre-bounded = [Marked] ; (addr | nonrw-fence |
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([R4rmb] ; fencerel(Rmb) ; [~Noreturn]))?
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let w-post-bounded = fence? ; [Marked] ; rmw-sequence
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let r-post-bounded = (nonrw-fence | ([~Noreturn] ; fencerel(Rmb) ; [R4rmb]))? ;
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[Marked]
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(* Visibility and executes-before for plain accesses *)
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let ww-vis = fence | (strong-fence ; xbstar ; w-pre-bounded) |
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(w-post-bounded ; vis ; w-pre-bounded)
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let wr-vis = fence | (strong-fence ; xbstar ; r-pre-bounded) |
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(w-post-bounded ; vis ; r-pre-bounded)
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let rw-xbstar = fence | (r-post-bounded ; xbstar ; w-pre-bounded)
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(* Potential races *)
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let pre-race = ext & ((Plain * M) | ((M \ IW) * Plain))
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(* Coherence requirements for plain accesses *)
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let wr-incoh = pre-race & rf & rw-xbstar^-1
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let rw-incoh = pre-race & fr & wr-vis^-1
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let ww-incoh = pre-race & co & ww-vis^-1
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empty (wr-incoh | rw-incoh | ww-incoh) as plain-coherence
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(* Actual races *)
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let ww-nonrace = ww-vis & ((Marked * W) | rw-xbstar) & ((W * Marked) | wr-vis)
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let ww-race = (pre-race & co) \ ww-nonrace
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let wr-race = (pre-race & (co? ; rf)) \ wr-vis \ rw-xbstar^-1
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let rw-race = (pre-race & fr) \ rw-xbstar
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flag ~empty (ww-race | wr-race | rw-race) as data-race
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