Linus Torvalds f3573b8f90 OpenRISC updates for v4.15 ... Small Things: - Move OpenRISC docs into Documentation and clean them up - Document previously undocumented devicetree bindings - Update the or1ksim dts to use stdout-path OpenRISC SMP support details: - First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get the architecture ready for SMP. - The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks" add the SMP locking infrastructure as needed. Using the qspinlocks and qrwlocks as suggested by Peter Z while reviewing the original spinlocks implementation. - The "support for ompic" adds a new irqchip device which is used for IPI communication to support SMP. - The "initial SMP support" adds smp.c and makes changes to all of the necessary data-structures to be per-cpu. - The remaining patches are bug fixes and debug helpers which I wanted to keep separate from the "initial SMP support" in order to allow them to be reviewed on their own. This includes: - add cacheflush support to fix icache aliasing - fix initial preempt state for secondary cpu tasks - sleep instead of spin on secondary wait - support framepointers and STACKTRACE_SUPPORT - enable LOCKDEP_SUPPORT and irqflags tracing - timer sync: Add tick timer sync logic - fix possible deadlock in timer sync, pointed out by mips guys Note: the irqchip patch was reviewed with Marc and we agreed to push it together with these patches. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJaCaO/AAoJEMOzHC1eZifkwyUQAIwp5q242D5P0Mo8gvpmNZ7s Lc7XBe1+dahbW8OIh0b8XhufkwFHY614bnrDBAr8GOcbaOXgxk8LbhTmkwbFO9z7 fm5YKr7il0dunCWfw278sQcZsCRQ9sQkXIei0gJL/56Uq6dbJhIREcOgjHBjDW5r tblrbv70fPmTCP/7cw08y4QwXIAf+8zEhECJcDKqFZ2nhQkWQUd3BAppxdCOWSDa aV9qOa/koP9lAKg8aWOCwCuS+WK386KNCCowsTxpyWdl9tMWsebeBh1odxteKiiB KpAENfEvbjuYMWH3CQ+XdSDDdIdGnIP6l5KDzBkhF1USXwS7AlaMUpbPHcLXVRFi 1S2zcO9i6WfTnaDpNZc+L8oHqgyLUDJ6RgC6juLEmbfnCVmzNkLKCYa3d3JRI/oC 6qxpHYkLKWsJoOHDcs0fiMOLhkJZrzPYkIv0fW+uwTM10onxhm48fm6RNWuwqXWd 4FoH8ufqeACxWEotv6pcL7RUYrmX1gmvxby8CCHiUBIBoRM3bGmqTVvgX64nULgB QIn/74R3J6GDPKicHDcq8ZOnMWvE6nbpXXbX73PqjXMf80HVjejV3Fg2su8m7LR0 +ni1ndKYB3V+t0+m1m5eMvpKMQ2HrMIMdx0M4xL+Z0fT8B3lcZWpb4wBsG7E+C49 pyf9xEk34Fe7HR+7KBO9 =euP7 -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://github.com/openrisc/linux Pull OpenRISC updates from Stafford Horne: "The OpenRISC work is a bit more interesting this time, adding SMP support and a few general cleanups. Small Things: - Move OpenRISC docs into Documentation and clean them up - Document previously undocumented devicetree bindings - Update the or1ksim dts to use stdout-path OpenRISC SMP support details: - First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get the architecture ready for SMP. - The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks" add the SMP locking infrastructure as needed. Using the qspinlocks and qrwlocks as suggested by Peter Z while reviewing the original spinlocks implementation. - The "support for ompic" adds a new irqchip device which is used for IPI communication to support SMP. - The "initial SMP support" adds smp.c and makes changes to all of the necessary data-structures to be per-cpu. The remaining patches are bug fixes and debug helpers which I wanted to keep separate from the "initial SMP support" in order to allow them to be reviewed on their own. This includes: - add cacheflush support to fix icache aliasing - fix initial preempt state for secondary cpu tasks - sleep instead of spin on secondary wait - support framepointers and STACKTRACE_SUPPORT - enable LOCKDEP_SUPPORT and irqflags tracing - timer sync: Add tick timer sync logic - fix possible deadlock in timer sync, pointed out by mips guys Note: the irqchip patch was reviewed with Marc and we agreed to push it together with these patches" * tag 'for-linus' of git://github.com/openrisc/linux: openrisc: fix possible deadlock scenario during timer sync openrisc: pass endianness info to sparse openrisc: add tick timer multi-core sync logic openrisc: enable LOCKDEP_SUPPORT and irqflags tracing openrisc: support framepointers and STACKTRACE_SUPPORT openrisc: add simple_smp dts and defconfig for simulators openrisc: add cacheflush support to fix icache aliasing openrisc: sleep instead of spin on secondary wait openrisc: fix initial preempt state for secondary cpu tasks openrisc: initial SMP support irqchip: add initial support for ompic dt-bindings: add openrisc to vendor prefixes list openrisc: use qspinlocks and qrwlocks openrisc: add 1 and 2 byte cmpxchg support openrisc: use shadow registers to save regs on exception dt-bindings: openrisc: Add OpenRISC platform SoC Documentation: openrisc: Updates to README Documentation: Move OpenRISC docs out of arch/ MAINTAINERS: Add OpenRISC pic maintainer openrisc: dts: or1ksim: Add stdout-path		2017-11-13 12:12:00 -08:00
..
delay.c	openrisc: initial SMP support	2017-11-03 14:01:13 +09:00
Makefile	openrisc: Add optimized memcpy routine	2017-02-25 04:14:36 +09:00
memcpy.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
memset.S	openrisc: Add optimized memset	2017-02-25 04:14:35 +09:00
string.S