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1e5907bcb3
Because the PWR_CTRL field is modeled as the power state of the DAC
widget, and at the same time it is used to implement mute/unmute, we
need some additional book-keeping to have the right end result no matter
the sequence of calls. Without this fix, one can mute an ongoing stream
by toggling a speaker pin control.
Fixes: 1a476abc72 ("tas2770: add tas2770 smart PA kernel driver")
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Link: https://lore.kernel.org/r/20220808141246.5749-5-povik+lin@cutebit.org
Signed-off-by: Mark Brown <broonie@kernel.org>
146 lines
5.4 KiB
C
146 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* ALSA SoC TAS2770 codec driver
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*
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* Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __TAS2770__
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#define __TAS2770__
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/* Book Control Register (available in page0 of each book) */
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#define TAS2770_BOOKCTL_PAGE 0
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#define TAS2770_BOOKCTL_REG 127
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#define TAS2770_REG(page, reg) ((page * 128) + reg)
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/* Page */
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#define TAS2770_PAGE TAS2770_REG(0X0, 0x00)
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#define TAS2770_PAGE_PAGE_MASK 255
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/* Software Reset */
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#define TAS2770_SW_RST TAS2770_REG(0X0, 0x01)
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#define TAS2770_RST BIT(0)
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/* Power Control */
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#define TAS2770_PWR_CTRL TAS2770_REG(0X0, 0x02)
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#define TAS2770_PWR_CTRL_MASK GENMASK(1, 0)
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#define TAS2770_PWR_CTRL_ACTIVE 0x0
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#define TAS2770_PWR_CTRL_MUTE BIT(0)
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#define TAS2770_PWR_CTRL_SHUTDOWN 0x2
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/* Playback Configuration Reg0 */
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#define TAS2770_PLAY_CFG_REG0 TAS2770_REG(0X0, 0x03)
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/* Playback Configuration Reg1 */
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#define TAS2770_PLAY_CFG_REG1 TAS2770_REG(0X0, 0x04)
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/* Playback Configuration Reg2 */
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#define TAS2770_PLAY_CFG_REG2 TAS2770_REG(0X0, 0x05)
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#define TAS2770_PLAY_CFG_REG2_VMAX 0xc9
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/* Misc Configuration Reg0 */
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#define TAS2770_MSC_CFG_REG0 TAS2770_REG(0X0, 0x07)
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/* TDM Configuration Reg0 */
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#define TAS2770_TDM_CFG_REG0 TAS2770_REG(0X0, 0x0A)
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#define TAS2770_TDM_CFG_REG0_SMP_MASK BIT(5)
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#define TAS2770_TDM_CFG_REG0_SMP_48KHZ 0x0
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#define TAS2770_TDM_CFG_REG0_SMP_44_1KHZ BIT(5)
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#define TAS2770_TDM_CFG_REG0_31_MASK GENMASK(3, 1)
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#define TAS2770_TDM_CFG_REG0_31_44_1_48KHZ 0x6
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#define TAS2770_TDM_CFG_REG0_31_88_2_96KHZ 0x8
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#define TAS2770_TDM_CFG_REG0_31_176_4_192KHZ 0xa
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#define TAS2770_TDM_CFG_REG0_FPOL_MASK BIT(0)
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#define TAS2770_TDM_CFG_REG0_FPOL_RSING 0
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#define TAS2770_TDM_CFG_REG0_FPOL_FALING 1
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/* TDM Configuration Reg1 */
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#define TAS2770_TDM_CFG_REG1 TAS2770_REG(0X0, 0x0B)
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#define TAS2770_TDM_CFG_REG1_MASK GENMASK(5, 1)
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#define TAS2770_TDM_CFG_REG1_51_SHIFT 1
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#define TAS2770_TDM_CFG_REG1_RX_MASK BIT(0)
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#define TAS2770_TDM_CFG_REG1_RX_RSING 0x0
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#define TAS2770_TDM_CFG_REG1_RX_FALING BIT(0)
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/* TDM Configuration Reg2 */
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#define TAS2770_TDM_CFG_REG2 TAS2770_REG(0X0, 0x0C)
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#define TAS2770_TDM_CFG_REG2_RXW_MASK GENMASK(3, 2)
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#define TAS2770_TDM_CFG_REG2_RXW_16BITS 0x0
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#define TAS2770_TDM_CFG_REG2_RXW_24BITS 0x8
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#define TAS2770_TDM_CFG_REG2_RXW_32BITS 0xc
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#define TAS2770_TDM_CFG_REG2_RXS_MASK GENMASK(1, 0)
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#define TAS2770_TDM_CFG_REG2_RXS_16BITS 0x0
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#define TAS2770_TDM_CFG_REG2_RXS_24BITS BIT(0)
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#define TAS2770_TDM_CFG_REG2_RXS_32BITS 0x2
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/* TDM Configuration Reg3 */
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#define TAS2770_TDM_CFG_REG3 TAS2770_REG(0X0, 0x0D)
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#define TAS2770_TDM_CFG_REG3_RXS_MASK GENMASK(7, 4)
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#define TAS2770_TDM_CFG_REG3_RXS_SHIFT 0x4
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#define TAS2770_TDM_CFG_REG3_30_MASK GENMASK(3, 0)
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#define TAS2770_TDM_CFG_REG3_30_SHIFT 0
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/* TDM Configuration Reg5 */
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#define TAS2770_TDM_CFG_REG5 TAS2770_REG(0X0, 0x0F)
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#define TAS2770_TDM_CFG_REG5_VSNS_MASK BIT(6)
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#define TAS2770_TDM_CFG_REG5_VSNS_ENABLE BIT(6)
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#define TAS2770_TDM_CFG_REG5_50_MASK GENMASK(5, 0)
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/* TDM Configuration Reg6 */
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#define TAS2770_TDM_CFG_REG6 TAS2770_REG(0X0, 0x10)
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#define TAS2770_TDM_CFG_REG6_ISNS_MASK BIT(6)
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#define TAS2770_TDM_CFG_REG6_ISNS_ENABLE BIT(6)
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#define TAS2770_TDM_CFG_REG6_50_MASK GENMASK(5, 0)
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/* Brown Out Prevention Reg0 */
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#define TAS2770_BO_PRV_REG0 TAS2770_REG(0X0, 0x1B)
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/* Interrupt MASK Reg0 */
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#define TAS2770_INT_MASK_REG0 TAS2770_REG(0X0, 0x20)
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#define TAS2770_INT_REG0_DEFAULT 0xfc
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#define TAS2770_INT_MASK_REG0_DISABLE 0xff
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/* Interrupt MASK Reg1 */
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#define TAS2770_INT_MASK_REG1 TAS2770_REG(0X0, 0x21)
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#define TAS2770_INT_REG1_DEFAULT 0xb1
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#define TAS2770_INT_MASK_REG1_DISABLE 0xff
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/* Live-Interrupt Reg0 */
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#define TAS2770_LVE_INT_REG0 TAS2770_REG(0X0, 0x22)
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/* Live-Interrupt Reg1 */
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#define TAS2770_LVE_INT_REG1 TAS2770_REG(0X0, 0x23)
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/* Latched-Interrupt Reg0 */
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#define TAS2770_LAT_INT_REG0 TAS2770_REG(0X0, 0x24)
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#define TAS2770_LAT_INT_REG0_OCE_FLG BIT(1)
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#define TAS2770_LAT_INT_REG0_OTE_FLG BIT(0)
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/* Latched-Interrupt Reg1 */
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#define TAS2770_LAT_INT_REG1 TAS2770_REG(0X0, 0x25)
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#define TAS2770_LAT_INT_REG1_VBA_TOV BIT(3)
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#define TAS2770_LAT_INT_REG1_VBA_TUV BIT(2)
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#define TAS2770_LAT_INT_REG1_BOUT_FLG BIT(1)
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/* VBAT MSB */
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#define TAS2770_VBAT_MSB TAS2770_REG(0X0, 0x27)
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/* VBAT LSB */
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#define TAS2770_VBAT_LSB TAS2770_REG(0X0, 0x28)
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/* TEMP MSB */
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#define TAS2770_TEMP_MSB TAS2770_REG(0X0, 0x29)
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/* TEMP LSB */
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#define TAS2770_TEMP_LSB TAS2770_REG(0X0, 0x2A)
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/* Interrupt Configuration */
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#define TAS2770_INT_CFG TAS2770_REG(0X0, 0x30)
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/* Misc IRQ */
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#define TAS2770_MISC_IRQ TAS2770_REG(0X0, 0x32)
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/* Clock Configuration */
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#define TAS2770_CLK_CGF TAS2770_REG(0X0, 0x3C)
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/* TDM Clock detection monitor */
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#define TAS2770_TDM_CLK_DETC TAS2770_REG(0X0, 0x77)
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/* Revision and PG ID */
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#define TAS2770_REV_AND_GPID TAS2770_REG(0X0, 0x7D)
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#define TAS2770_POWER_ACTIVE 0
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#define TAS2770_POWER_MUTE BIT(0)
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#define TAS2770_POWER_SHUTDOWN BIT(1)
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#define ERROR_OVER_CURRENT BIT(0)
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#define ERROR_DIE_OVERTEMP BIT(1)
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#define ERROR_OVER_VOLTAGE BIT(2)
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#define ERROR_UNDER_VOLTAGE BIT(3)
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#define ERROR_BROWNOUT BIT(4)
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#define ERROR_CLASSD_PWR BIT(5)
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struct tas2770_priv {
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struct snd_soc_component *component;
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struct gpio_desc *reset_gpio;
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struct gpio_desc *sdz_gpio;
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struct regmap *regmap;
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struct device *dev;
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int v_sense_slot;
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int i_sense_slot;
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bool dac_powered;
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bool unmuted;
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};
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#endif /* __TAS2770__ */
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