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This patch adds support for checking if the digital baseband (DB) System-on-Chip (aka "cpu) ASIC hardware version is 1.0, 1.1 or 2.0. We print the result in the bootlog, the functions are then used for runtime decisions based on hardware version. Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/*
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* Copyright (C) 2009 ST-Ericsson.
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*
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* U8500 hardware definitions
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_HARDWARE_H
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#define __MACH_HARDWARE_H
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/* macros to get at IO space when running virtually
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* We dont map all the peripherals, let ioremap do
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* this for us. We map only very basic peripherals here.
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*/
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#define U8500_IO_VIRTUAL 0xf0000000
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#define U8500_IO_PHYSICAL 0xa0000000
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/* this macro is used in assembly, so no cast */
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#define IO_ADDRESS(x) \
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(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
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/* typesafe io address */
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#define __io_address(n) __io(IO_ADDRESS(n))
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/* used by some plat-nomadik code */
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#define io_p2v(n) __io_address(n)
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#include <mach/db8500-regs.h>
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#include <mach/db5500-regs.h>
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#ifdef CONFIG_UX500_SOC_DB8500
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#define UX500(periph) U8500_##periph##_BASE
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#elif defined(CONFIG_UX500_SOC_DB5500)
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#define UX500(periph) U5500_##periph##_BASE
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#endif
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#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0)
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#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1)
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#define UX500_B2R2_BASE UX500(B2R2)
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#define UX500_CLKRST1_BASE UX500(CLKRST1)
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#define UX500_CLKRST2_BASE UX500(CLKRST2)
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#define UX500_CLKRST3_BASE UX500(CLKRST3)
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#define UX500_CLKRST5_BASE UX500(CLKRST5)
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#define UX500_CLKRST6_BASE UX500(CLKRST6)
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#define UX500_DMA_BASE UX500(DMA)
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#define UX500_FSMC_BASE UX500(FSMC)
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#define UX500_GIC_CPU_BASE UX500(GIC_CPU)
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#define UX500_GIC_DIST_BASE UX500(GIC_DIST)
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#define UX500_I2C1_BASE UX500(I2C1)
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#define UX500_I2C2_BASE UX500(I2C2)
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#define UX500_I2C3_BASE UX500(I2C3)
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#define UX500_L2CC_BASE UX500(L2CC)
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#define UX500_MCDE_BASE UX500(MCDE)
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#define UX500_MTU0_BASE UX500(MTU0)
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#define UX500_MTU1_BASE UX500(MTU1)
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#define UX500_PRCMU_BASE UX500(PRCMU)
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#define UX500_RNG_BASE UX500(RNG)
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#define UX500_RTC_BASE UX500(RTC)
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#define UX500_SCU_BASE UX500(SCU)
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#define UX500_SDI0_BASE UX500(SDI0)
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#define UX500_SDI1_BASE UX500(SDI1)
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#define UX500_SDI2_BASE UX500(SDI2)
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#define UX500_SDI3_BASE UX500(SDI3)
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#define UX500_SDI4_BASE UX500(SDI4)
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#define UX500_SPI0_BASE UX500(SPI0)
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#define UX500_SPI1_BASE UX500(SPI1)
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#define UX500_SPI2_BASE UX500(SPI2)
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#define UX500_SPI3_BASE UX500(SPI3)
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#define UX500_SIA_BASE UX500(SIA)
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#define UX500_SVA_BASE UX500(SVA)
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#define UX500_TWD_BASE UX500(TWD)
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#define UX500_UART0_BASE UX500(UART0)
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#define UX500_UART1_BASE UX500(UART1)
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#define UX500_UART2_BASE UX500(UART2)
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#define UX500_USBOTG_BASE UX500(USBOTG)
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/* ST-Ericsson modified pl022 id */
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#define SSP_PER_ID 0x01080022
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#ifndef __ASSEMBLY__
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#include <asm/cputype.h>
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static inline bool cpu_is_u8500(void)
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{
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#ifdef CONFIG_UX500_SOC_DB8500
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return 1;
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#else
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return 0;
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#endif
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}
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#define CPUID_DB8500ED 0x410fc090
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#define CPUID_DB8500V1 0x411fc091
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#define CPUID_DB8500V2 0x412fc091
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static inline bool cpu_is_u8500ed(void)
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{
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return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED);
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}
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static inline bool cpu_is_u8500v1(void)
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{
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return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1);
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}
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static inline bool cpu_is_u8500v2(void)
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{
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return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2);
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}
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#ifdef CONFIG_UX500_SOC_DB8500
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bool cpu_is_u8500v10(void);
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bool cpu_is_u8500v11(void);
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bool cpu_is_u8500v20(void);
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#else
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static inline bool cpu_is_u8500v10(void) { return false; }
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static inline bool cpu_is_u8500v11(void) { return false; }
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static inline bool cpu_is_u8500v20(void) { return false; }
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#endif
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static inline bool cpu_is_u5500(void)
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{
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#ifdef CONFIG_UX500_SOC_DB5500
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return 1;
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#else
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return 0;
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#endif
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}
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#endif
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#endif /* __MACH_HARDWARE_H */
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