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6a12235c7d
There seems to be no reason for these -- they're a 1:1 mapping on all platforms. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
479 lines
12 KiB
C
479 lines
12 KiB
C
/*
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* Transmeta's Efficeon AGPGART driver.
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*
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* Based upon a diff by Linus around November '02.
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*
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* Ported to the 2.6 kernel by Carlos Puchol <cpglinux@puchol.com>
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* and H. Peter Anvin <hpa@transmeta.com>.
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*/
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/*
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* NOTE-cpg-040217:
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*
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* - when compiled as a module, after loading the module,
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* it will refuse to unload, indicating it is in use,
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* when it is not.
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* - no s3 (suspend to ram) testing.
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* - tested on the efficeon integrated nothbridge for tens
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* of iterations of starting x and glxgears.
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* - tested with radeon 9000 and radeon mobility m9 cards
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* - tested with c3/c4 enabled (with the mobility m9 card)
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <linux/gfp.h>
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#include <linux/page-flags.h>
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#include <linux/mm.h>
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#include "agp.h"
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/*
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* The real differences to the generic AGP code is
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* in the GART mappings - a two-level setup with the
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* first level being an on-chip 64-entry table.
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*
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* The page array is filled through the ATTPAGE register
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* (Aperture Translation Table Page Register) at 0xB8. Bits:
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* 31:20: physical page address
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* 11:9: Page Attribute Table Index (PATI)
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* must match the PAT index for the
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* mapped pages (the 2nd level page table pages
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* themselves should be just regular WB-cacheable,
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* so this is normally zero.)
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* 8: Present
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* 7:6: reserved, write as zero
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* 5:0: GATT directory index: which 1st-level entry
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*
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* The Efficeon AGP spec requires pages to be WB-cacheable
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* but to be explicitly CLFLUSH'd after any changes.
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*/
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#define EFFICEON_ATTPAGE 0xb8
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#define EFFICEON_L1_SIZE 64 /* Number of PDE pages */
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#define EFFICEON_PATI (0 << 9)
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#define EFFICEON_PRESENT (1 << 8)
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static struct _efficeon_private {
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unsigned long l1_table[EFFICEON_L1_SIZE];
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} efficeon_private;
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static const struct gatt_mask efficeon_generic_masks[] =
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{
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{.mask = 0x00000001, .type = 0}
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};
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/* This function does the same thing as mask_memory() for this chipset... */
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static inline unsigned long efficeon_mask_memory(struct page *page)
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{
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unsigned long addr = page_to_phys(page);
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return addr | 0x00000001;
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}
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static const struct aper_size_info_lvl2 efficeon_generic_sizes[4] =
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{
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{256, 65536, 0},
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{128, 32768, 32},
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{64, 16384, 48},
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{32, 8192, 56}
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};
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/*
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* Control interfaces are largely identical to
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* the legacy Intel 440BX..
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*/
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static int efficeon_fetch_size(void)
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{
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int i;
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u16 temp;
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struct aper_size_info_lvl2 *values;
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pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
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values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static void efficeon_tlbflush(struct agp_memory * mem)
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{
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printk(KERN_DEBUG PFX "efficeon_tlbflush()\n");
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
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}
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static void efficeon_cleanup(void)
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{
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u16 temp;
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struct aper_size_info_lvl2 *previous_size;
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printk(KERN_DEBUG PFX "efficeon_cleanup()\n");
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previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
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pci_write_config_word(agp_bridge->dev, INTEL_APSIZE,
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previous_size->size_value);
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}
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static int efficeon_configure(void)
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{
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u32 temp;
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u16 temp2;
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struct aper_size_info_lvl2 *current_size;
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printk(KERN_DEBUG PFX "efficeon_configure()\n");
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current_size = A_SIZE_LVL2(agp_bridge->current_size);
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/* aperture size */
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pci_write_config_word(agp_bridge->dev, INTEL_APSIZE,
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current_size->size_value);
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* agpctrl */
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pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
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/* paccfg/nbxcfg */
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pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
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pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
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(temp2 & ~(1 << 10)) | (1 << 9) | (1 << 11));
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/* clear any possible error conditions */
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pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
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return 0;
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}
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static int efficeon_free_gatt_table(struct agp_bridge_data *bridge)
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{
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int index, freed = 0;
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for (index = 0; index < EFFICEON_L1_SIZE; index++) {
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unsigned long page = efficeon_private.l1_table[index];
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if (page) {
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efficeon_private.l1_table[index] = 0;
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ClearPageReserved(virt_to_page((char *)page));
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free_page(page);
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freed++;
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}
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printk(KERN_DEBUG PFX "efficeon_free_gatt_table(%p, %02x, %08x)\n",
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agp_bridge->dev, EFFICEON_ATTPAGE, index);
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pci_write_config_dword(agp_bridge->dev,
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EFFICEON_ATTPAGE, index);
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}
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printk(KERN_DEBUG PFX "efficeon_free_gatt_table() freed %d pages\n", freed);
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return 0;
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}
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/*
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* Since we don't need contiguous memory we just try
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* to get the gatt table once
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*/
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#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
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#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
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GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
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#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
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#undef GET_GATT
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#define GET_GATT(addr) (efficeon_private.gatt_pages[\
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GET_PAGE_DIR_IDX(addr)]->remapped)
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static int efficeon_create_gatt_table(struct agp_bridge_data *bridge)
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{
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int index;
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const int pati = EFFICEON_PATI;
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const int present = EFFICEON_PRESENT;
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const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
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int num_entries, l1_pages;
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num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
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printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries);
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/* There are 2^10 PTE pages per PDE page */
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BUG_ON(num_entries & 0x3ff);
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l1_pages = num_entries >> 10;
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for (index = 0 ; index < l1_pages ; index++) {
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int offset;
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unsigned long page;
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unsigned long value;
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page = efficeon_private.l1_table[index];
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BUG_ON(page);
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page = get_zeroed_page(GFP_KERNEL);
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if (!page) {
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efficeon_free_gatt_table(agp_bridge);
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return -ENOMEM;
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}
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SetPageReserved(virt_to_page((char *)page));
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for (offset = 0; offset < PAGE_SIZE; offset += clflush_chunk)
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clflush((char *)page+offset);
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efficeon_private.l1_table[index] = page;
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value = virt_to_phys((unsigned long *)page) | pati | present | index;
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pci_write_config_dword(agp_bridge->dev,
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EFFICEON_ATTPAGE, value);
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}
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return 0;
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}
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static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
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{
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int i, count = mem->page_count, num_entries;
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unsigned int *page, *last_page;
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const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
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const unsigned long clflush_mask = ~(clflush_chunk-1);
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printk(KERN_DEBUG PFX "efficeon_insert_memory(%lx, %d)\n", pg_start, count);
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num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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if (type != 0 || mem->type != 0)
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return -EINVAL;
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if (!mem->is_flushed) {
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global_cache_flush();
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mem->is_flushed = true;
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}
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last_page = NULL;
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for (i = 0; i < count; i++) {
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int index = pg_start + i;
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unsigned long insert = efficeon_mask_memory(mem->pages[i]);
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page = (unsigned int *) efficeon_private.l1_table[index >> 10];
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if (!page)
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continue;
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page += (index & 0x3ff);
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*page = insert;
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/* clflush is slow, so don't clflush until we have to */
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if (last_page &&
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(((unsigned long)page^(unsigned long)last_page) &
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clflush_mask))
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clflush(last_page);
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last_page = page;
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}
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if ( last_page )
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clflush(last_page);
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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}
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static int efficeon_remove_memory(struct agp_memory * mem, off_t pg_start, int type)
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{
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int i, count = mem->page_count, num_entries;
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printk(KERN_DEBUG PFX "efficeon_remove_memory(%lx, %d)\n", pg_start, count);
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num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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if (type != 0 || mem->type != 0)
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return -EINVAL;
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for (i = 0; i < count; i++) {
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int index = pg_start + i;
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unsigned int *page = (unsigned int *) efficeon_private.l1_table[index >> 10];
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if (!page)
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continue;
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page += (index & 0x3ff);
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*page = 0;
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}
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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}
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static const struct agp_bridge_driver efficeon_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = efficeon_generic_sizes,
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.size_type = LVL2_APER_SIZE,
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.num_aperture_sizes = 4,
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.configure = efficeon_configure,
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.fetch_size = efficeon_fetch_size,
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.cleanup = efficeon_cleanup,
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.tlb_flush = efficeon_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = efficeon_generic_masks,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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// Efficeon-specific GATT table setup / populate / teardown
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.create_gatt_table = efficeon_create_gatt_table,
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.free_gatt_table = efficeon_free_gatt_table,
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.insert_memory = efficeon_insert_memory,
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.remove_memory = efficeon_remove_memory,
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.cant_use_aperture = false, // true might be faster?
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// Generic
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static int __devinit agp_efficeon_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_bridge_data *bridge;
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u8 cap_ptr;
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struct resource *r;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return -ENODEV;
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/* Probe for Efficeon controller */
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if (pdev->device != PCI_DEVICE_ID_EFFICEON) {
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printk(KERN_ERR PFX "Unsupported Efficeon chipset (device id: %04x)\n",
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pdev->device);
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return -ENODEV;
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}
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printk(KERN_INFO PFX "Detected Transmeta Efficeon TM8000 series chipset\n");
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->driver = &efficeon_driver;
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bridge->dev = pdev;
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bridge->capndx = cap_ptr;
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/*
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* The following fixes the case where the BIOS has "forgotten" to
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* provide an address range for the GART.
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* 20030610 - hamish@zot.org
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*/
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r = &pdev->resource[0];
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if (!r->start && r->end) {
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if (pci_assign_resource(pdev, 0)) {
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printk(KERN_ERR PFX "could not assign resource 0\n");
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agp_put_bridge(bridge);
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return -ENODEV;
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}
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}
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/*
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* If the device has not been properly setup, the following will catch
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* the problem and should stop the system from crashing.
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* 20030610 - hamish@zot.org
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*/
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if (pci_enable_device(pdev)) {
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printk(KERN_ERR PFX "Unable to Enable PCI device\n");
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agp_put_bridge(bridge);
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return -ENODEV;
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}
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/* Fill in the mode register */
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if (cap_ptr) {
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pci_read_config_dword(pdev,
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bridge->capndx+PCI_AGP_STATUS,
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&bridge->mode);
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}
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pci_set_drvdata(pdev, bridge);
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return agp_add_bridge(bridge);
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}
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static void __devexit agp_efficeon_remove(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
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agp_remove_bridge(bridge);
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agp_put_bridge(bridge);
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}
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#ifdef CONFIG_PM
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static int agp_efficeon_suspend(struct pci_dev *dev, pm_message_t state)
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{
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return 0;
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}
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static int agp_efficeon_resume(struct pci_dev *pdev)
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{
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printk(KERN_DEBUG PFX "agp_efficeon_resume()\n");
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return efficeon_configure();
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}
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#endif
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static struct pci_device_id agp_efficeon_pci_table[] = {
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_TRANSMETA,
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.device = PCI_ANY_ID,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(pci, agp_efficeon_pci_table);
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static struct pci_driver agp_efficeon_pci_driver = {
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.name = "agpgart-efficeon",
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.id_table = agp_efficeon_pci_table,
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.probe = agp_efficeon_probe,
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.remove = agp_efficeon_remove,
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#ifdef CONFIG_PM
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.suspend = agp_efficeon_suspend,
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.resume = agp_efficeon_resume,
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#endif
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};
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static int __init agp_efficeon_init(void)
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{
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static int agp_initialised=0;
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if (agp_off)
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return -EINVAL;
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if (agp_initialised == 1)
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return 0;
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agp_initialised=1;
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return pci_register_driver(&agp_efficeon_pci_driver);
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}
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static void __exit agp_efficeon_cleanup(void)
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{
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pci_unregister_driver(&agp_efficeon_pci_driver);
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}
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module_init(agp_efficeon_init);
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module_exit(agp_efficeon_cleanup);
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MODULE_AUTHOR("Carlos Puchol <cpglinux@puchol.com>");
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MODULE_LICENSE("GPL and additional rights");
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