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percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
577 lines
15 KiB
C
577 lines
15 KiB
C
/*
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* AMD K7 AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <linux/page-flags.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include "agp.h"
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#define AMD_MMBASE 0x14
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#define AMD_APSIZE 0xac
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#define AMD_MODECNTL 0xb0
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#define AMD_MODECNTL2 0xb2
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#define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
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#define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
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#define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
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#define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
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static struct pci_device_id agp_amdk7_pci_table[];
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struct amd_page_map {
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unsigned long *real;
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unsigned long __iomem *remapped;
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};
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static struct _amd_irongate_private {
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volatile u8 __iomem *registers;
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struct amd_page_map **gatt_pages;
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int num_tables;
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} amd_irongate_private;
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static int amd_create_page_map(struct amd_page_map *page_map)
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{
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int i;
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page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
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if (page_map->real == NULL)
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return -ENOMEM;
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#ifndef CONFIG_X86
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SetPageReserved(virt_to_page(page_map->real));
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global_cache_flush();
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page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
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PAGE_SIZE);
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if (page_map->remapped == NULL) {
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ClearPageReserved(virt_to_page(page_map->real));
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free_page((unsigned long) page_map->real);
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page_map->real = NULL;
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return -ENOMEM;
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}
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global_cache_flush();
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#else
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set_memory_uc((unsigned long)page_map->real, 1);
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page_map->remapped = page_map->real;
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#endif
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for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
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writel(agp_bridge->scratch_page, page_map->remapped+i);
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readl(page_map->remapped+i); /* PCI Posting. */
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}
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return 0;
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}
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static void amd_free_page_map(struct amd_page_map *page_map)
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{
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#ifndef CONFIG_X86
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iounmap(page_map->remapped);
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ClearPageReserved(virt_to_page(page_map->real));
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#else
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set_memory_wb((unsigned long)page_map->real, 1);
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#endif
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free_page((unsigned long) page_map->real);
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}
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static void amd_free_gatt_pages(void)
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{
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int i;
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struct amd_page_map **tables;
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struct amd_page_map *entry;
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tables = amd_irongate_private.gatt_pages;
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for (i = 0; i < amd_irongate_private.num_tables; i++) {
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entry = tables[i];
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if (entry != NULL) {
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if (entry->real != NULL)
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amd_free_page_map(entry);
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kfree(entry);
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}
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}
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kfree(tables);
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amd_irongate_private.gatt_pages = NULL;
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}
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static int amd_create_gatt_pages(int nr_tables)
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{
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struct amd_page_map **tables;
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struct amd_page_map *entry;
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int retval = 0;
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int i;
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tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
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if (tables == NULL)
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return -ENOMEM;
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for (i = 0; i < nr_tables; i++) {
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entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
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tables[i] = entry;
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if (entry == NULL) {
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retval = -ENOMEM;
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break;
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}
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retval = amd_create_page_map(entry);
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if (retval != 0)
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break;
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}
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amd_irongate_private.num_tables = i;
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amd_irongate_private.gatt_pages = tables;
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if (retval != 0)
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amd_free_gatt_pages();
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return retval;
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}
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/* Since we don't need contiguous memory we just try
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* to get the gatt table once
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*/
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#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
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#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
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GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
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#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
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#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
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GET_PAGE_DIR_IDX(addr)]->remapped)
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static int amd_create_gatt_table(struct agp_bridge_data *bridge)
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{
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struct aper_size_info_lvl2 *value;
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struct amd_page_map page_dir;
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unsigned long addr;
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int retval;
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u32 temp;
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int i;
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value = A_SIZE_LVL2(agp_bridge->current_size);
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retval = amd_create_page_map(&page_dir);
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if (retval != 0)
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return retval;
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retval = amd_create_gatt_pages(value->num_entries / 1024);
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if (retval != 0) {
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amd_free_page_map(&page_dir);
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return retval;
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}
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agp_bridge->gatt_table_real = (u32 *)page_dir.real;
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agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
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agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
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/* Get the address for the gart region.
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* This is a bus address even on the alpha, b/c its
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* used to program the agp master not the cpu
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*/
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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agp_bridge->gart_bus_addr = addr;
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/* Calculate the agp offset */
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for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
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writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
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page_dir.remapped+GET_PAGE_DIR_OFF(addr));
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readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
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}
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return 0;
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}
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static int amd_free_gatt_table(struct agp_bridge_data *bridge)
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{
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struct amd_page_map page_dir;
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page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
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page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
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amd_free_gatt_pages();
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amd_free_page_map(&page_dir);
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return 0;
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}
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static int amd_irongate_fetch_size(void)
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{
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int i;
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u32 temp;
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struct aper_size_info_lvl2 *values;
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pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
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temp = (temp & 0x0000000e);
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values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int amd_irongate_configure(void)
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{
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struct aper_size_info_lvl2 *current_size;
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u32 temp;
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u16 enable_reg;
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current_size = A_SIZE_LVL2(agp_bridge->current_size);
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if (!amd_irongate_private.registers) {
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/* Get the memory mapped registers */
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pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
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temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
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if (!amd_irongate_private.registers)
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return -ENOMEM;
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}
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/* Write out the address of the gatt table */
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writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
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readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
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/* Write the Sync register */
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pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
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/* Set indexing mode */
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pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
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/* Write the enable register */
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enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
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enable_reg = (enable_reg | 0x0004);
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writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
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readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
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/* Write out the size register */
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pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
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temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
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pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
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/* Flush the tlb */
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writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
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readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
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return 0;
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}
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static void amd_irongate_cleanup(void)
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{
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struct aper_size_info_lvl2 *previous_size;
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u32 temp;
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u16 enable_reg;
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previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
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enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
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enable_reg = (enable_reg & ~(0x0004));
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writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
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readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
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/* Write back the previous size and disable gart translation */
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pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
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temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
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pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
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iounmap((void __iomem *) amd_irongate_private.registers);
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}
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/*
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* This routine could be implemented by taking the addresses
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* written to the GATT, and flushing them individually. However
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* currently it just flushes the whole table. Which is probably
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* more efficent, since agp_memory blocks can be a large number of
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* entries.
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*/
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static void amd_irongate_tlbflush(struct agp_memory *temp)
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{
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writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
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readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
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}
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static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i, j, num_entries;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
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if (type != 0 || mem->type != 0)
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return -EINVAL;
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if ((pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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j = pg_start;
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while (j < (pg_start + mem->page_count)) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
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return -EBUSY;
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j++;
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}
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if (!mem->is_flushed) {
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global_cache_flush();
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mem->is_flushed = true;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_generic_mask_memory(agp_bridge,
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page_to_phys(mem->pages[i]),
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mem->type),
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cur_gatt+GET_GATT_OFF(addr));
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readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
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}
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amd_irongate_tlbflush(mem);
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return 0;
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}
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static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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if (type != 0 || mem->type != 0)
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return -EINVAL;
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
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readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
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}
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amd_irongate_tlbflush(mem);
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return 0;
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}
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static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
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{
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{2048, 524288, 0x0000000c},
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{1024, 262144, 0x0000000a},
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{512, 131072, 0x00000008},
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{256, 65536, 0x00000006},
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{128, 32768, 0x00000004},
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{64, 16384, 0x00000002},
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{32, 8192, 0x00000000}
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};
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static const struct gatt_mask amd_irongate_masks[] =
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{
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{.mask = 1, .type = 0}
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};
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static const struct agp_bridge_driver amd_irongate_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = amd_irongate_sizes,
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.size_type = LVL2_APER_SIZE,
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.num_aperture_sizes = 7,
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.configure = amd_irongate_configure,
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.fetch_size = amd_irongate_fetch_size,
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.cleanup = amd_irongate_cleanup,
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.tlb_flush = amd_irongate_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = amd_irongate_masks,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = amd_create_gatt_table,
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.free_gatt_table = amd_free_gatt_table,
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.insert_memory = amd_insert_memory,
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.remove_memory = amd_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
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{
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{
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.device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
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.chipset_name = "Irongate",
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},
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{
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.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
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.chipset_name = "761",
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},
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{
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.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
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.chipset_name = "760MP",
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},
|
|
{ }, /* dummy final entry, always present */
|
|
};
|
|
|
|
static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct agp_bridge_data *bridge;
|
|
u8 cap_ptr;
|
|
int j;
|
|
|
|
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
|
|
if (!cap_ptr)
|
|
return -ENODEV;
|
|
|
|
j = ent - agp_amdk7_pci_table;
|
|
dev_info(&pdev->dev, "AMD %s chipset\n",
|
|
amd_agp_device_ids[j].chipset_name);
|
|
|
|
bridge = agp_alloc_bridge();
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
bridge->driver = &amd_irongate_driver;
|
|
bridge->dev_private_data = &amd_irongate_private,
|
|
bridge->dev = pdev;
|
|
bridge->capndx = cap_ptr;
|
|
|
|
/* 751 Errata (22564_B-1.PDF)
|
|
erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
|
|
system controller may experience noise due to strong drive strengths
|
|
*/
|
|
if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
|
|
struct pci_dev *gfxcard=NULL;
|
|
|
|
cap_ptr = 0;
|
|
while (!cap_ptr) {
|
|
gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
|
|
if (!gfxcard) {
|
|
dev_info(&pdev->dev, "no AGP VGA controller\n");
|
|
return -ENODEV;
|
|
}
|
|
cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
|
|
}
|
|
|
|
/* With so many variants of NVidia cards, it's simpler just
|
|
to blacklist them all, and then whitelist them as needed
|
|
(if necessary at all). */
|
|
if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
|
|
agp_bridge->flags |= AGP_ERRATA_1X;
|
|
dev_info(&pdev->dev, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
|
|
}
|
|
pci_dev_put(gfxcard);
|
|
}
|
|
|
|
/* 761 Errata (23613_F.pdf)
|
|
* Revisions B0/B1 were a disaster.
|
|
* erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
|
|
* erratum 45: Timing problem prevents fast writes -- Disable fast write.
|
|
* erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
|
|
* With this lot disabled, we should prevent lockups. */
|
|
if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
|
|
if (pdev->revision == 0x10 || pdev->revision == 0x11) {
|
|
agp_bridge->flags = AGP_ERRATA_FASTWRITES;
|
|
agp_bridge->flags |= AGP_ERRATA_SBA;
|
|
agp_bridge->flags |= AGP_ERRATA_1X;
|
|
dev_info(&pdev->dev, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
|
|
}
|
|
}
|
|
|
|
/* Fill in the mode register */
|
|
pci_read_config_dword(pdev,
|
|
bridge->capndx+PCI_AGP_STATUS,
|
|
&bridge->mode);
|
|
|
|
pci_set_drvdata(pdev, bridge);
|
|
return agp_add_bridge(bridge);
|
|
}
|
|
|
|
static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
agp_remove_bridge(bridge);
|
|
agp_put_bridge(bridge);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int agp_amdk7_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
pci_save_state(pdev);
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int agp_amdk7_resume(struct pci_dev *pdev)
|
|
{
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
|
|
return amd_irongate_driver.configure();
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
/* must be the same order as name table above */
|
|
static struct pci_device_id agp_amdk7_pci_table[] = {
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
|
|
|
|
static struct pci_driver agp_amdk7_pci_driver = {
|
|
.name = "agpgart-amdk7",
|
|
.id_table = agp_amdk7_pci_table,
|
|
.probe = agp_amdk7_probe,
|
|
.remove = agp_amdk7_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = agp_amdk7_suspend,
|
|
.resume = agp_amdk7_resume,
|
|
#endif
|
|
};
|
|
|
|
static int __init agp_amdk7_init(void)
|
|
{
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
return pci_register_driver(&agp_amdk7_pci_driver);
|
|
}
|
|
|
|
static void __exit agp_amdk7_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&agp_amdk7_pci_driver);
|
|
}
|
|
|
|
module_init(agp_amdk7_init);
|
|
module_exit(agp_amdk7_cleanup);
|
|
|
|
MODULE_LICENSE("GPL and additional rights");
|