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3e72771e21
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> |
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| .. | ||
| clk-audio-sync.c | ||
| clk-divider.c | ||
| clk-periph-gate.c | ||
| clk-periph.c | ||
| clk-pll-out.c | ||
| clk-pll.c | ||
| clk-super.c | ||
| clk-tegra20.c | ||
| clk-tegra30.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||