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a5a1d1c291
There is no point in having an extra type for extra confusion. u64 is unambiguous. Conversion was done with the following coccinelle script: @rem@ @@ -typedef u64 cycle_t; @fix@ typedef cycle_t; @@ -cycle_t +u64 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: John Stultz <john.stultz@linaro.org>
462 lines
12 KiB
C
462 lines
12 KiB
C
/*
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* DaVinci timer subsystem
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <mach/cputype.h>
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#include <mach/hardware.h>
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#include <mach/time.h>
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#include "clock.h"
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static struct clock_event_device clockevent_davinci;
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static unsigned int davinci_clock_tick_rate;
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/*
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* This driver configures the 2 64-bit count-up timers as 4 independent
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* 32-bit count-up timers used as follows:
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*/
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enum {
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TID_CLOCKEVENT,
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TID_CLOCKSOURCE,
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};
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/* Timer register offsets */
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#define PID12 0x0
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#define TIM12 0x10
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#define TIM34 0x14
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#define PRD12 0x18
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#define PRD34 0x1c
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#define TCR 0x20
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#define TGCR 0x24
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#define WDTCR 0x28
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/* Offsets of the 8 compare registers */
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#define CMP12_0 0x60
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#define CMP12_1 0x64
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#define CMP12_2 0x68
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#define CMP12_3 0x6c
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#define CMP12_4 0x70
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#define CMP12_5 0x74
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#define CMP12_6 0x78
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#define CMP12_7 0x7c
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/* Timer register bitfields */
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#define TCR_ENAMODE_DISABLE 0x0
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#define TCR_ENAMODE_ONESHOT 0x1
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#define TCR_ENAMODE_PERIODIC 0x2
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#define TCR_ENAMODE_MASK 0x3
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#define TGCR_TIMMODE_SHIFT 2
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#define TGCR_TIMMODE_64BIT_GP 0x0
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#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
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#define TGCR_TIMMODE_64BIT_WDOG 0x2
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#define TGCR_TIMMODE_32BIT_CHAINED 0x3
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#define TGCR_TIM12RS_SHIFT 0
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#define TGCR_TIM34RS_SHIFT 1
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#define TGCR_RESET 0x0
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#define TGCR_UNRESET 0x1
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#define TGCR_RESET_MASK 0x3
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#define WDTCR_WDEN_SHIFT 14
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#define WDTCR_WDEN_DISABLE 0x0
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#define WDTCR_WDEN_ENABLE 0x1
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#define WDTCR_WDKEY_SHIFT 16
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#define WDTCR_WDKEY_SEQ0 0xa5c6
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#define WDTCR_WDKEY_SEQ1 0xda7e
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struct timer_s {
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char *name;
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unsigned int id;
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unsigned long period;
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unsigned long opts;
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unsigned long flags;
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void __iomem *base;
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unsigned long tim_off;
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unsigned long prd_off;
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unsigned long enamode_shift;
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struct irqaction irqaction;
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};
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static struct timer_s timers[];
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/* values for 'opts' field of struct timer_s */
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#define TIMER_OPTS_DISABLED 0x01
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#define TIMER_OPTS_ONESHOT 0x02
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#define TIMER_OPTS_PERIODIC 0x04
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#define TIMER_OPTS_STATE_MASK 0x07
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#define TIMER_OPTS_USE_COMPARE 0x80000000
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#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
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static char *id_to_name[] = {
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[T0_BOT] = "timer0_0",
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[T0_TOP] = "timer0_1",
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[T1_BOT] = "timer1_0",
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[T1_TOP] = "timer1_1",
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};
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static int timer32_config(struct timer_s *t)
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{
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u32 tcr;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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if (USING_COMPARE(t)) {
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struct davinci_timer_instance *dtip =
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soc_info->timer_info->timers;
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int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
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/*
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* Next interrupt should be the current time reg value plus
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* the new period (using 32-bit unsigned addition/wrapping
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* to 0 on overflow). This assumes that the clocksource
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* is setup to count to 2^32-1 before wrapping around to 0.
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*/
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__raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
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t->base + dtip[event_timer].cmp_off);
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} else {
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tcr = __raw_readl(t->base + TCR);
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/* disable timer */
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tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
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__raw_writel(tcr, t->base + TCR);
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/* reset counter to zero, set new period */
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__raw_writel(0, t->base + t->tim_off);
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__raw_writel(t->period, t->base + t->prd_off);
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/* Set enable mode */
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if (t->opts & TIMER_OPTS_ONESHOT)
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tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
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else if (t->opts & TIMER_OPTS_PERIODIC)
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tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
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__raw_writel(tcr, t->base + TCR);
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}
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return 0;
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}
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static inline u32 timer32_read(struct timer_s *t)
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{
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return __raw_readl(t->base + t->tim_off);
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_davinci;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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/* called when 32-bit counter wraps */
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static irqreturn_t freerun_interrupt(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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static struct timer_s timers[] = {
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[TID_CLOCKEVENT] = {
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.name = "clockevent",
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.opts = TIMER_OPTS_DISABLED,
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.irqaction = {
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.flags = IRQF_TIMER,
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.handler = timer_interrupt,
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}
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},
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[TID_CLOCKSOURCE] = {
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.name = "free-run counter",
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.period = ~0,
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.opts = TIMER_OPTS_PERIODIC,
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.irqaction = {
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.flags = IRQF_TIMER,
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.handler = freerun_interrupt,
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}
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},
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};
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static void __init timer_init(void)
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{
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
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void __iomem *base[2];
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int i;
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/* Global init of each 64-bit timer as a whole */
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for(i=0; i<2; i++) {
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u32 tgcr;
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base[i] = ioremap(dtip[i].base, SZ_4K);
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if (WARN_ON(!base[i]))
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continue;
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/* Disabled, Internal clock source */
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__raw_writel(0, base[i] + TCR);
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/* reset both timers, no pre-scaler for timer34 */
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tgcr = 0;
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__raw_writel(tgcr, base[i] + TGCR);
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/* Set both timers to unchained 32-bit */
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tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
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__raw_writel(tgcr, base[i] + TGCR);
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/* Unreset timers */
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tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
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__raw_writel(tgcr, base[i] + TGCR);
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/* Init both counters to zero */
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__raw_writel(0, base[i] + TIM12);
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__raw_writel(0, base[i] + TIM34);
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}
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/* Init of each timer as a 32-bit timer */
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for (i=0; i< ARRAY_SIZE(timers); i++) {
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struct timer_s *t = &timers[i];
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int timer = ID_TO_TIMER(t->id);
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u32 irq;
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t->base = base[timer];
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if (!t->base)
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continue;
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if (IS_TIMER_BOT(t->id)) {
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t->enamode_shift = 6;
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t->tim_off = TIM12;
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t->prd_off = PRD12;
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irq = dtip[timer].bottom_irq;
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} else {
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t->enamode_shift = 22;
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t->tim_off = TIM34;
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t->prd_off = PRD34;
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irq = dtip[timer].top_irq;
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}
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/* Register interrupt */
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t->irqaction.name = t->name;
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t->irqaction.dev_id = (void *)t;
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if (t->irqaction.handler != NULL) {
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irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
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setup_irq(irq, &t->irqaction);
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}
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}
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}
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/*
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* clocksource
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*/
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static u64 read_cycles(struct clocksource *cs)
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{
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struct timer_s *t = &timers[TID_CLOCKSOURCE];
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return (cycles_t)timer32_read(t);
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}
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static struct clocksource clocksource_davinci = {
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.rating = 300,
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.read = read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* Overwrite weak default sched_clock with something more precise
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*/
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static u64 notrace davinci_read_sched_clock(void)
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{
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return timer32_read(&timers[TID_CLOCKSOURCE]);
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}
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/*
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* clockevent
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*/
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static int davinci_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct timer_s *t = &timers[TID_CLOCKEVENT];
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t->period = cycles;
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timer32_config(t);
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return 0;
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}
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static int davinci_shutdown(struct clock_event_device *evt)
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{
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struct timer_s *t = &timers[TID_CLOCKEVENT];
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t->opts &= ~TIMER_OPTS_STATE_MASK;
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t->opts |= TIMER_OPTS_DISABLED;
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return 0;
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}
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static int davinci_set_oneshot(struct clock_event_device *evt)
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{
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struct timer_s *t = &timers[TID_CLOCKEVENT];
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t->opts &= ~TIMER_OPTS_STATE_MASK;
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t->opts |= TIMER_OPTS_ONESHOT;
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return 0;
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}
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static int davinci_set_periodic(struct clock_event_device *evt)
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{
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struct timer_s *t = &timers[TID_CLOCKEVENT];
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t->period = davinci_clock_tick_rate / (HZ);
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t->opts &= ~TIMER_OPTS_STATE_MASK;
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t->opts |= TIMER_OPTS_PERIODIC;
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timer32_config(t);
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return 0;
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}
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static struct clock_event_device clockevent_davinci = {
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = davinci_set_next_event,
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.set_state_shutdown = davinci_shutdown,
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.set_state_periodic = davinci_set_periodic,
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.set_state_oneshot = davinci_set_oneshot,
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};
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void __init davinci_timer_init(void)
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{
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struct clk *timer_clk;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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unsigned int clockevent_id;
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unsigned int clocksource_id;
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int i;
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clockevent_id = soc_info->timer_info->clockevent_id;
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clocksource_id = soc_info->timer_info->clocksource_id;
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timers[TID_CLOCKEVENT].id = clockevent_id;
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timers[TID_CLOCKSOURCE].id = clocksource_id;
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/*
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* If using same timer for both clock events & clocksource,
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* a compare register must be used to generate an event interrupt.
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* This is equivalent to a oneshot timer only (not periodic).
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*/
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if (clockevent_id == clocksource_id) {
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struct davinci_timer_instance *dtip =
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soc_info->timer_info->timers;
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int event_timer = ID_TO_TIMER(clockevent_id);
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/* Only bottom timers can use compare regs */
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if (IS_TIMER_TOP(clockevent_id))
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pr_warn("%s: Invalid use of system timers. Results unpredictable.\n",
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__func__);
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else if ((dtip[event_timer].cmp_off == 0)
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|| (dtip[event_timer].cmp_irq == 0))
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pr_warn("%s: Invalid timer instance setup. Results unpredictable.\n",
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__func__);
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else {
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timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
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clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
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}
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}
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timer_clk = clk_get(NULL, "timer0");
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BUG_ON(IS_ERR(timer_clk));
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clk_prepare_enable(timer_clk);
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/* init timer hw */
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timer_init();
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davinci_clock_tick_rate = clk_get_rate(timer_clk);
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/* setup clocksource */
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clocksource_davinci.name = id_to_name[clocksource_id];
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if (clocksource_register_hz(&clocksource_davinci,
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davinci_clock_tick_rate))
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pr_err("%s: can't register clocksource!\n",
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clocksource_davinci.name);
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sched_clock_register(davinci_read_sched_clock, 32,
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davinci_clock_tick_rate);
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/* setup clockevent */
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clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
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clockevent_davinci.cpumask = cpumask_of(0);
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clockevents_config_and_register(&clockevent_davinci,
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davinci_clock_tick_rate, 1, 0xfffffffe);
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for (i=0; i< ARRAY_SIZE(timers); i++)
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timer32_config(&timers[i]);
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}
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/* reset board using watchdog timer */
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void davinci_watchdog_reset(struct platform_device *pdev)
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{
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u32 tgcr, wdtcr;
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void __iomem *base;
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struct clk *wd_clk;
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base = ioremap(pdev->resource[0].start, SZ_4K);
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if (WARN_ON(!base))
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return;
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wd_clk = clk_get(&pdev->dev, NULL);
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if (WARN_ON(IS_ERR(wd_clk)))
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return;
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clk_prepare_enable(wd_clk);
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/* disable, internal clock source */
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__raw_writel(0, base + TCR);
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/* reset timer, set mode to 64-bit watchdog, and unreset */
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tgcr = 0;
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__raw_writel(tgcr, base + TGCR);
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tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
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tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
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__raw_writel(tgcr, base + TGCR);
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/* clear counter and period regs */
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__raw_writel(0, base + TIM12);
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__raw_writel(0, base + TIM34);
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__raw_writel(0, base + PRD12);
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__raw_writel(0, base + PRD34);
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/* put watchdog in pre-active state */
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wdtcr = __raw_readl(base + WDTCR);
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wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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__raw_writel(wdtcr, base + WDTCR);
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/* put watchdog in active state */
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wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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__raw_writel(wdtcr, base + WDTCR);
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/* write an invalid value to the WDKEY field to trigger
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* a watchdog reset */
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wdtcr = 0x00004000;
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__raw_writel(wdtcr, base + WDTCR);
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}
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