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e6500 core performance monitors has the following features: - 6 performance monitor counters - 512 events supported - no threshold events e6500 PMU has more specific events (Data L1 cache misses, Instruction L1 cache misses, etc ) than e500 PMU (which only had Data L1 cache reloads, etc). Where available, the more specific events have been used which will produce slightly different results than e500 PMU equivalents. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> |
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| .. | ||
| bhrb.S | ||
| callchain.c | ||
| core-book3s.c | ||
| core-fsl-emb.c | ||
| e500-pmu.c | ||
| e6500-pmu.c | ||
| Makefile | ||
| mpc7450-pmu.c | ||
| power4-pmu.c | ||
| power5-pmu.c | ||
| power5+-pmu.c | ||
| power6-pmu.c | ||
| power7-pmu.c | ||
| power8-pmu.c | ||
| ppc970-pmu.c | ||