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f0f59a00a1
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
111 lines
4.1 KiB
C
111 lines
4.1 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_GUC_REG_H_
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#define _I915_GUC_REG_H_
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/* Definitions of GuC H/W registers, bits, etc */
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#define GUC_STATUS _MMIO(0xc000)
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#define GS_BOOTROM_SHIFT 1
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#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
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#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
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#define GS_UKERNEL_SHIFT 8
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#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
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#define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT)
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#define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT)
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#define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT)
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#define GS_MIA_SHIFT 16
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#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
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#define GS_MIA_CORE_STATE (1 << GS_MIA_SHIFT)
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#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
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#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
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#define UOS_RSA_SCRATCH_MAX_COUNT 64
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#define DMA_ADDR_0_LOW _MMIO(0xc300)
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#define DMA_ADDR_0_HIGH _MMIO(0xc304)
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#define DMA_ADDR_1_LOW _MMIO(0xc308)
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#define DMA_ADDR_1_HIGH _MMIO(0xc30c)
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#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
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#define DMA_ADDRESS_SPACE_GTT (8 << 16)
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#define DMA_COPY_SIZE _MMIO(0xc310)
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#define DMA_CTRL _MMIO(0xc314)
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#define UOS_MOVE (1<<4)
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#define START_DMA (1<<0)
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#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
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#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
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#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
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#define GUC_WOPCM_SIZE _MMIO(0xc050)
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#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
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/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
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#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
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#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
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#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
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#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
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#define GT_DOORBELL_ENABLE (1<<0)
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#define GEN8_GTCR _MMIO(0x4274)
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#define GEN8_GTCR_INVALIDATE (1<<0)
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#define GUC_ARAT_C6DIS _MMIO(0xA178)
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#define GUC_SHIM_CONTROL _MMIO(0xc064)
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#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
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#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
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#define GUC_ENABLE_MIA_CACHING (1<<2)
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#define GUC_GEN10_MSGCH_ENABLE (1<<4)
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#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
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#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
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#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
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#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
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#define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES | \
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GUC_ENABLE_READ_CACHE_LOGIC | \
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GUC_ENABLE_MIA_CACHING | \
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GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \
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GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \
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GUC_ENABLE_MIA_CLOCK_GATING)
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#define HOST2GUC_INTERRUPT _MMIO(0xc4c8)
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#define HOST2GUC_TRIGGER (1<<0)
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#define DRBMISC1 0x1984
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#define DOORBELL_ENABLE (1<<0)
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#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
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#define GEN8_DRB_VALID (1<<0)
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#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
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#define DE_GUCRMR _MMIO(0x44054)
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#define GUC_BCS_RCS_IER _MMIO(0xC550)
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#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
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#define GUC_WD_VECS_IER _MMIO(0xC558)
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#define GUC_PM_P24C_IER _MMIO(0xC55C)
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#endif
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