Guo Ren 3b756ccddb csky: Fix TLB maintenance synchronization problem ... TLB invalidate didn't contain a barrier operation in csky cpu and we need to prevent previous PTW response after TLB invalidation instruction. Of cause, the ASID changing also needs to take care of the issue. CPU0 CPU1 =============== =============== set_pte sync_is() -> See the previous set_pte for all harts tlbi.vas -> Invalidate all harts TLB entry & flush pipeline Signed-off-by: Guo Ren <guoren@linux.alibaba.com>		2021-01-12 09:52:41 +08:00
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inc/abi	csky: Fix TLB maintenance synchronization problem	2021-01-12 09:52:41 +08:00
alignment.c	csky: Support kernel non-aligned access	2019-08-20 20:15:44 +08:00
bswapdi.c	csky: Library functions	2018-10-26 00:54:24 +08:00
bswapsi.c	csky: Library functions	2018-10-26 00:54:24 +08:00
cacheflush.c	csky: Fixup 610 vipt cache flush mechanism	2019-08-22 10:44:24 +08:00
Makefile	csky: Fixup abiv1 memset error	2019-07-19 14:21:36 +08:00
memcpy.S	csky: Library functions	2018-10-26 00:54:24 +08:00
mmap.c	csky: Fixup arch_get_unmapped_area() implementation	2019-08-20 16:09:37 +08:00
strksyms.c	csky: Fixup abiv1 memset error	2019-07-19 14:21:36 +08:00