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6e32fedc8b
Abuses existing gpuobj_new() chan argument for this, which in turn forces all NVOBJ_FLAG_VM allocations to be done from the global heap, not suballocated from the channel's private heap. Not a problem though in practise. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
244 lines
7.0 KiB
C
244 lines
7.0 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_util.h"
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#include "nouveau_vm.h"
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#include "nouveau_ramht.h"
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#include "nvc0_copy.fuc.h"
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struct nvc0_copy_engine {
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struct nouveau_exec_engine base;
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u32 irq;
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u32 pmc;
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u32 fuc;
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u32 ctx;
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};
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static int
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nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin;
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struct nouveau_gpuobj *ctx = NULL;
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int ret;
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ret = nouveau_gpuobj_new(dev, chan, 256, 256,
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NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER |
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NVOBJ_FLAG_ZERO_ALLOC, &ctx);
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if (ret)
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return ret;
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nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->linst));
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nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->linst));
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dev_priv->engine.instmem.flush(dev);
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chan->engctx[engine] = ctx;
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return 0;
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}
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static int
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nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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return 0;
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}
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static void
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nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
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struct nouveau_gpuobj *ctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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u32 inst;
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inst = (chan->ramin->vinst >> 12);
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inst |= 0x40000000;
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/* disable fifo access */
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nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
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/* mark channel as unloaded if it's currently active */
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if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
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nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
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/* mark next channel as invalid if it's about to be loaded */
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if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
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nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
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/* restore fifo access */
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nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);
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nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
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nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);
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nouveau_gpuobj_ref(NULL, &ctx);
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chan->engctx[engine] = ctx;
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}
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static int
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nvc0_copy_init(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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int i;
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nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
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nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
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nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
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nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
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for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
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nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);
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nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
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for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
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nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
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}
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nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
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nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
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nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
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nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
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return 0;
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}
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static int
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nvc0_copy_fini(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);
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/* trigger fuc context unload */
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nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
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nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
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nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
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nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);
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nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
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return 0;
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}
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static struct nouveau_enum nvc0_copy_isr_error_name[] = {
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{ 0x0001, "ILLEGAL_MTHD" },
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{ 0x0002, "INVALID_ENUM" },
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{ 0x0003, "INVALID_BITFIELD" },
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{}
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};
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static void
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nvc0_copy_isr(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
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u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
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u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
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u32 chid = nvc0_graph_isr_chid(dev, inst);
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u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
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u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
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u32 mthd = (addr & 0x07ff) << 2;
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u32 subc = (addr & 0x3800) >> 11;
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u32 data = nv_rd32(dev, pcopy->fuc + 0x044);
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if (stat & 0x00000040) {
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NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
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nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
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printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
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chid, inst, subc, mthd, data);
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nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
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stat &= ~0x00000040;
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}
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if (stat) {
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NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
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nv_wr32(dev, pcopy->fuc + 0x004, stat);
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}
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}
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static void
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nvc0_copy_isr_0(struct drm_device *dev)
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{
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nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
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}
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static void
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nvc0_copy_isr_1(struct drm_device *dev)
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{
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nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
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}
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static void
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nvc0_copy_destroy(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, pcopy->irq);
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if (engine == NVOBJ_ENGINE_COPY0)
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NVOBJ_ENGINE_DEL(dev, COPY0);
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else
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NVOBJ_ENGINE_DEL(dev, COPY1);
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kfree(pcopy);
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}
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int
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nvc0_copy_create(struct drm_device *dev, int engine)
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{
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struct nvc0_copy_engine *pcopy;
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pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
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if (!pcopy)
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return -ENOMEM;
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pcopy->base.destroy = nvc0_copy_destroy;
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pcopy->base.init = nvc0_copy_init;
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pcopy->base.fini = nvc0_copy_fini;
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pcopy->base.context_new = nvc0_copy_context_new;
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pcopy->base.context_del = nvc0_copy_context_del;
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pcopy->base.object_new = nvc0_copy_object_new;
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if (engine == 0) {
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pcopy->irq = 5;
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pcopy->pmc = 0x00000040;
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pcopy->fuc = 0x104000;
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pcopy->ctx = 0x0230;
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nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
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NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
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NVOBJ_CLASS(dev, 0x90b5, COPY0);
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} else {
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pcopy->irq = 6;
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pcopy->pmc = 0x00000080;
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pcopy->fuc = 0x105000;
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pcopy->ctx = 0x0240;
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nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
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NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
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NVOBJ_CLASS(dev, 0x90b8, COPY1);
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}
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return 0;
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}
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