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296e583e99
The new clkctrl data layout for am33xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
320 lines
12 KiB
C
320 lines
12 KiB
C
/*
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* AM33XX Clock init
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*
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* Copyright (C) 2013 Texas Instruments, Inc
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* Tero Kristo (t-kristo@ti.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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#include <dt-bindings/clock/am3.h>
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#include "clock.h"
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static const char * const am3_gpio1_dbclk_parents[] __initconst = {
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"clk-24mhz-clkctrl:0000:0",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
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{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
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{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
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{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
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{ AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
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{ AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
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{ AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
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{ AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
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{ AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
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{ AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
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{ AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
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{ AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
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{ AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
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{ AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
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{ AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
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{ AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
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{ AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
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{ AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
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{ AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
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{ AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
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{ AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
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{ AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
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{ AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
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{ AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
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{ AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
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{ AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
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{ AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
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{ AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
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{ AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
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{ AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
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{ 0 },
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};
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static const char * const am3_gpio0_dbclk_parents[] __initconst = {
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"gpio0_dbclk_mux_ck",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
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{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
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{ AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
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{ AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
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{ AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
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{ AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
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{ AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
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{ AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
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{ AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
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{ AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
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{ AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
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{ AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
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{ 0 },
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};
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static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
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"sys_clkin_ck",
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NULL,
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};
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static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
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"l3-aon-clkctrl:0000:19",
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"l3-aon-clkctrl:0000:30",
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NULL,
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};
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static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
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"l3-aon-clkctrl:0000:20",
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NULL,
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};
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static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
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.max_div = 64,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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};
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static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
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"l3-aon-clkctrl:0000:22",
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NULL,
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};
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static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
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.max_div = 64,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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};
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static const char * const am3_dbg_clka_ck_parents[] __initconst = {
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"dpll_core_m4_ck",
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NULL,
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};
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static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
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{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
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{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
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{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
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{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
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{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
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{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
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{ AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
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{ AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
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{ AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
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{ AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
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{ AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
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{ 0 },
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};
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static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
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{ AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
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{ 0 },
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};
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const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
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{ 0x44e00038, am3_l4ls_clkctrl_regs },
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{ 0x44e0001c, am3_l3s_clkctrl_regs },
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{ 0x44e00024, am3_l3_clkctrl_regs },
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{ 0x44e00120, am3_l4hs_clkctrl_regs },
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{ 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
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{ 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
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{ 0x44e00018, am3_lcdc_clkctrl_regs },
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{ 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
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{ 0x44e00400, am3_l4_wkup_clkctrl_regs },
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{ 0x44e00414, am3_l3_aon_clkctrl_regs },
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{ 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
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{ 0x44e00600, am3_mpu_clkctrl_regs },
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{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
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{ 0x44e00900, am3_gfx_l3_clkctrl_regs },
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{ 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
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{ 0 },
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};
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static struct ti_dt_clk am33xx_clks[] = {
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DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
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DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
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DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
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DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
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DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
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DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
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DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
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DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
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DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
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DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
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DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
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DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
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DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
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{ .node_name = NULL },
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};
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static const char *enable_init_clks[] = {
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"dpll_ddr_m2_ck",
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"dpll_mpu_m2_ck",
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"l3_gclk",
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"l4hs_gclk",
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"l4fw_gclk",
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"l4ls_gclk",
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/* Required for external peripherals like, Audio codecs */
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"clkout2_ck",
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};
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int __init am33xx_dt_clk_init(void)
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{
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struct clk *clk1, *clk2;
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
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ti_dt_clocks_register(am33xx_compat_clks);
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else
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ti_dt_clocks_register(am33xx_clks);
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omap2_clk_disable_autoidle_all();
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ti_clk_add_aliases();
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omap2_clk_enable_init_clocks(enable_init_clks,
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ARRAY_SIZE(enable_init_clks));
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/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
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* physically present, in such a case HWMOD enabling of
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* clock would be failure with default parent. And timer
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* probe thinks clock is already enabled, this leads to
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* crash upon accessing timer 3 & 6 registers in probe.
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* Fix by setting parent of both these timers to master
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* oscillator clock.
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*/
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clk1 = clk_get_sys(NULL, "sys_clkin_ck");
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clk2 = clk_get_sys(NULL, "timer3_fck");
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clk_set_parent(clk2, clk1);
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clk2 = clk_get_sys(NULL, "timer6_fck");
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clk_set_parent(clk2, clk1);
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/*
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* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
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* the design/spec, so as a result, for example, timer which supposed
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* to get expired @60Sec, but will expire somewhere ~@40Sec, which is
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* not expected by any use-case, so change WDT1 clock source to PRCM
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* 32KHz clock.
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*/
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clk1 = clk_get_sys(NULL, "wdt1_fck");
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clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
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clk_set_parent(clk1, clk2);
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return 0;
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}
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