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Similar to the syndrome calculation, the recovery algorithms also work on 64 bytes at a time to align with the L1 cache line size of current and future LoongArch cores (that we care about). Which means unrolled-by-4 LSX and unrolled-by-2 LASX code. The assembly is originally based on the x86 SSSE3/AVX2 ports, but register allocation has been redone to take advantage of LSX/LASX's 32 vector registers, and instruction sequence has been optimized to suit (e.g. LoongArch can perform per-byte srl and andi on vectors, but x86 cannot). Performance numbers measured by instrumenting the raid6test code, on a 3A5000 system clocked at 2.5GHz: > lasx 2data: 354.987 MiB/s > lasx datap: 350.430 MiB/s > lsx 2data: 340.026 MiB/s > lsx datap: 337.318 MiB/s > intx1 2data: 164.280 MiB/s > intx1 datap: 187.966 MiB/s Because recovery algorithms are chosen solely based on priority and availability, lasx is marked as priority 2 and lsx priority 1. At least for the current generation of LoongArch micro-architectures, LASX should always be faster than LSX whenever supported, and have similar power consumption characteristics (because the only known LASX-capable uarch, the LA464, always compute the full 256-bit result for vector ops). Acked-by: Song Liu <song@kernel.org> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> |
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| .. | ||
| test | ||
| .gitignore | ||
| algos.c | ||
| altivec.uc | ||
| avx2.c | ||
| avx512.c | ||
| int.uc | ||
| loongarch_simd.c | ||
| loongarch.h | ||
| Makefile | ||
| mktables.c | ||
| mmx.c | ||
| neon.c | ||
| neon.h | ||
| neon.uc | ||
| recov_avx2.c | ||
| recov_avx512.c | ||
| recov_loongarch_simd.c | ||
| recov_neon_inner.c | ||
| recov_neon.c | ||
| recov_s390xc.c | ||
| recov_ssse3.c | ||
| recov.c | ||
| s390vx.uc | ||
| sse1.c | ||
| sse2.c | ||
| unroll.awk | ||
| vpermxor.uc | ||
| x86.h | ||