Lyude 39748841a7 drm/i915/skl: Fix typo in DPLL_CFGCR1 definition ... We accidentally point both cfgcr registers for the second shared DPLL to the same location in i915_reg.h. This results in a lot of hw pipe state mismatches whenever we try to do a modeset that requires allocating the DPLL to a CRTC: [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x80000168, found 0x000004a5) [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 108000, found 49500) [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 108000, found 49500) This usually ends up causing blank monitors, since the DPLL never can get set to the right clock. Fixes: 086f8e84a0 ("drm/i915: Prefix raw register defines with underscore") Signed-off-by: Lyude <cpaul@redhat.com> Cc: drm-intel-fixes@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1454600601-21900-1-git-send-email-cpaul@redhat.com (cherry picked from commit da3b891b0f) Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2016-02-10 18:02:42 +02:00
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drm	drm/i915/skl: Fix typo in DPLL_CFGCR1 definition	2016-02-10 18:02:42 +02:00
host1x	gpu: host1x: Add Tegra210 support	2015-12-14 10:50:33 +01:00
ipu-v3	Merge branch 'patchwork' into v4l_for_linus	2016-01-11 11:13:27 -02:00
vga	More power management and ACPI updates for v4.5-rc1	2016-01-20 19:06:49 -08:00
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