mirror of
https://github.com/torvalds/linux.git
synced 2024-12-26 04:42:12 +00:00
b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
307 lines
6.7 KiB
Plaintext
307 lines
6.7 KiB
Plaintext
/*
|
|
* STX GP3 - 8560 ADS Device Tree Source
|
|
*
|
|
* Copyright 2008 Freescale Semiconductor Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "stx,gp3";
|
|
compatible = "stx,gp3-8560", "stx,gp3";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
ethernet0 = &enet0;
|
|
ethernet1 = &enet1;
|
|
serial0 = &serial0;
|
|
pci0 = &pci0;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
PowerPC,8560@0 {
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
d-cache-line-size = <32>;
|
|
i-cache-line-size = <32>;
|
|
d-cache-size = <32768>;
|
|
i-cache-size = <32768>;
|
|
timebase-frequency = <0>;
|
|
bus-frequency = <0>;
|
|
clock-frequency = <0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x10000000>;
|
|
};
|
|
|
|
soc@fdf00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
ranges = <0 0xfdf00000 0x100000>;
|
|
bus-frequency = <0>;
|
|
compatible = "fsl,mpc8560-immr", "simple-bus";
|
|
|
|
ecm-law@0 {
|
|
compatible = "fsl,ecm-law";
|
|
reg = <0x0 0x1000>;
|
|
fsl,num-laws = <8>;
|
|
};
|
|
|
|
ecm@1000 {
|
|
compatible = "fsl,mpc8560-ecm", "fsl,ecm";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <17 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
memory-controller@2000 {
|
|
compatible = "fsl,mpc8540-memory-controller";
|
|
reg = <0x2000 0x1000>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <18 2>;
|
|
};
|
|
|
|
L2: l2-cache-controller@20000 {
|
|
compatible = "fsl,mpc8540-l2-cache-controller";
|
|
reg = <0x20000 0x1000>;
|
|
cache-line-size = <32>;
|
|
cache-size = <0x40000>; // L2, 256K
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <16 2>;
|
|
};
|
|
|
|
i2c@3000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3000 0x100>;
|
|
interrupts = <43 2>;
|
|
interrupt-parent = <&mpic>;
|
|
dfsrr;
|
|
};
|
|
|
|
dma@21300 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
|
|
reg = <0x21300 0x4>;
|
|
ranges = <0x0 0x21100 0x200>;
|
|
cell-index = <0>;
|
|
dma-channel@0 {
|
|
compatible = "fsl,mpc8560-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x0 0x80>;
|
|
cell-index = <0>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <20 2>;
|
|
};
|
|
dma-channel@80 {
|
|
compatible = "fsl,mpc8560-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x80 0x80>;
|
|
cell-index = <1>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <21 2>;
|
|
};
|
|
dma-channel@100 {
|
|
compatible = "fsl,mpc8560-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x100 0x80>;
|
|
cell-index = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <22 2>;
|
|
};
|
|
dma-channel@180 {
|
|
compatible = "fsl,mpc8560-dma-channel",
|
|
"fsl,eloplus-dma-channel";
|
|
reg = <0x180 0x80>;
|
|
cell-index = <3>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <23 2>;
|
|
};
|
|
};
|
|
|
|
enet0: ethernet@24000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <0>;
|
|
device_type = "network";
|
|
model = "TSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x24000 0x1000>;
|
|
ranges = <0x0 0x24000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <29 2 30 2 34 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi0>;
|
|
phy-handle = <&phy2>;
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-mdio";
|
|
reg = <0x520 0x20>;
|
|
|
|
phy2: ethernet-phy@2 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <5 4>;
|
|
reg = <2>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
phy4: ethernet-phy@4 {
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <5 4>;
|
|
reg = <4>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
tbi0: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
enet1: ethernet@25000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
cell-index = <1>;
|
|
device_type = "network";
|
|
model = "TSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x25000 0x1000>;
|
|
ranges = <0x0 0x25000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <35 2 36 2 40 2>;
|
|
interrupt-parent = <&mpic>;
|
|
tbi-handle = <&tbi1>;
|
|
phy-handle = <&phy4>;
|
|
|
|
mdio@520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-tbi";
|
|
reg = <0x520 0x20>;
|
|
|
|
tbi1: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
};
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "chrp,open-pic";
|
|
device_type = "open-pic";
|
|
};
|
|
|
|
cpm@919c0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
|
|
reg = <0x919c0 0x30>;
|
|
ranges;
|
|
|
|
muram@80000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x80000 0x10000>;
|
|
|
|
data@0 {
|
|
compatible = "fsl,cpm-muram-data";
|
|
reg = <0 0x4000 0x9000 0x2000>;
|
|
};
|
|
};
|
|
|
|
brg@919f0 {
|
|
compatible = "fsl,mpc8560-brg",
|
|
"fsl,cpm2-brg",
|
|
"fsl,cpm-brg";
|
|
reg = <0x919f0 0x10 0x915f0 0x10>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
cpmpic: pic@90c00 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <46 2>;
|
|
interrupt-parent = <&mpic>;
|
|
reg = <0x90c00 0x80>;
|
|
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
|
};
|
|
|
|
serial0: serial@91a20 {
|
|
device_type = "serial";
|
|
compatible = "fsl,mpc8560-scc-uart",
|
|
"fsl,cpm2-scc-uart";
|
|
reg = <0x91a20 0x20 0x88100 0x100>;
|
|
fsl,cpm-brg = <2>;
|
|
fsl,cpm-command = <0x4a00000>;
|
|
interrupts = <41 8>;
|
|
interrupt-parent = <&cpmpic>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pci0: pci@fdf08000 {
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
|
|
/* IDSEL 0x0c */
|
|
0x6000 0 0 1 &mpic 1 1
|
|
0x6000 0 0 2 &mpic 2 1
|
|
0x6000 0 0 3 &mpic 3 1
|
|
0x6000 0 0 4 &mpic 4 1
|
|
|
|
/* IDSEL 0x0d */
|
|
0x6800 0 0 1 &mpic 4 1
|
|
0x6800 0 0 2 &mpic 1 1
|
|
0x6800 0 0 3 &mpic 2 1
|
|
0x6800 0 0 4 &mpic 3 1
|
|
|
|
/* IDSEL 0x0e */
|
|
0x7000 0 0 1 &mpic 3 1
|
|
0x7000 0 0 2 &mpic 4 1
|
|
0x7000 0 0 3 &mpic 1 1
|
|
0x7000 0 0 4 &mpic 2 1
|
|
|
|
/* IDSEL 0x0f */
|
|
0x7800 0 0 1 &mpic 2 1
|
|
0x7800 0 0 2 &mpic 3 1
|
|
0x7800 0 0 3 &mpic 4 1
|
|
0x7800 0 0 4 &mpic 1 1>;
|
|
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <24 2>;
|
|
bus-range = <0 0>;
|
|
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
|
0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
|
|
clock-frequency = <66666666>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xfdf08000 0x1000>;
|
|
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
|
device_type = "pci";
|
|
};
|
|
};
|