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53d3ff7be4
8a3400x device implements its own reg_read and reg_write, which only supports I2C bus access. This patch adds support for SMBus access. Signed-off-by: Min Li <min.li.xe@renesas.com> Link: https://lore.kernel.org/r/LV3P220MB12021342F302AADEB6C1601CA0192@LV3P220MB1202.NAMP220.PROD.OUTLOOK.COM Signed-off-by: Lee Jones <lee@kernel.org>
286 lines
6.9 KiB
C
286 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SPI driver for Renesas Synchronization Management Unit (SMU) devices.
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*
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* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/rsmu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include "rsmu.h"
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#define RSMU_CM_PAGE_ADDR 0x7C
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#define RSMU_SABRE_PAGE_ADDR 0x7F
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#define RSMU_PAGE_MASK 0xFFFFFF80
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#define RSMU_ADDR_MASK 0x7F
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static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
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{
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struct spi_device *client = to_spi_device(rsmu->dev);
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struct spi_transfer xfer = {0};
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struct spi_message msg;
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u8 cmd[RSMU_MAX_READ_COUNT + 1] = {0};
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u8 rsp[RSMU_MAX_READ_COUNT + 1] = {0};
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int ret;
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if (bytes > RSMU_MAX_READ_COUNT)
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return -EINVAL;
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cmd[0] = reg | 0x80;
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xfer.rx_buf = rsp;
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xfer.len = bytes + 1;
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xfer.tx_buf = cmd;
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xfer.bits_per_word = client->bits_per_word;
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xfer.speed_hz = client->max_speed_hz;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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/*
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* 4-wire SPI is a shift register, so for every byte you send,
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* you get one back at the same time. Example read from 0xC024,
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* which has value of 0x2D
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*
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* MOSI:
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* 7C 00 C0 #Set page register
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* A4 00 #MSB is set, so this is read command
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* MISO:
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* XX 2D #XX is a dummy byte from sending A4 and we
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* need to throw it away
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*/
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ret = spi_sync(client, &msg);
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if (ret >= 0)
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memcpy(buf, &rsp[1], xfer.len-1);
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return ret;
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}
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static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes)
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{
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struct spi_device *client = to_spi_device(rsmu->dev);
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struct spi_transfer xfer = {0};
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struct spi_message msg;
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u8 cmd[RSMU_MAX_WRITE_COUNT + 1] = {0};
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if (bytes > RSMU_MAX_WRITE_COUNT)
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return -EINVAL;
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cmd[0] = reg;
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memcpy(&cmd[1], buf, bytes);
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xfer.len = bytes + 1;
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xfer.tx_buf = cmd;
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xfer.bits_per_word = client->bits_per_word;
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xfer.speed_hz = client->max_speed_hz;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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return spi_sync(client, &msg);
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}
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/*
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* 1-byte (1B) offset addressing:
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* 16-bit register address: the lower 7 bits of the register address come
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* from the offset addr byte and the upper 9 bits come from the page register.
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*/
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static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u32 reg)
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{
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u8 page_reg;
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u8 buf[4];
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u16 bytes;
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u32 page;
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int err;
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switch (rsmu->type) {
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case RSMU_CM:
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/* Do not modify page register for none-scsr registers */
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if (reg < RSMU_CM_SCSR_BASE)
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return 0;
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page_reg = RSMU_CM_PAGE_ADDR;
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page = reg & RSMU_PAGE_MASK;
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buf[0] = (u8)(page & 0xFF);
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buf[1] = (u8)((page >> 8) & 0xFF);
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buf[2] = (u8)((page >> 16) & 0xFF);
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buf[3] = (u8)((page >> 24) & 0xFF);
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bytes = 4;
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break;
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case RSMU_SABRE:
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/* Do not modify page register if reg is page register itself */
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if ((reg & RSMU_ADDR_MASK) == RSMU_ADDR_MASK)
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return 0;
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page_reg = RSMU_SABRE_PAGE_ADDR;
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page = reg & RSMU_PAGE_MASK;
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/* The three page bits are located in the single Page Register */
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buf[0] = (u8)((page >> 7) & 0x7);
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bytes = 1;
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break;
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default:
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dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
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return -ENODEV;
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}
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/* Simply return if we are on the same page */
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if (rsmu->page == page)
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return 0;
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err = rsmu_write_device(rsmu, page_reg, buf, bytes);
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if (err)
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dev_err(rsmu->dev, "Failed to set page offset 0x%x\n", page);
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else
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/* Remember the last page */
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rsmu->page = page;
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return err;
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}
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static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
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u8 addr = (u8)(reg & RSMU_ADDR_MASK);
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int err;
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err = rsmu_write_page_register(rsmu, reg);
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if (err)
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return err;
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err = rsmu_read_device(rsmu, addr, (u8 *)val, 1);
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if (err)
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dev_err(rsmu->dev, "Failed to read offset address 0x%x\n", addr);
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return err;
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}
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static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val)
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{
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struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context);
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u8 addr = (u8)(reg & RSMU_ADDR_MASK);
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u8 data = (u8)val;
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int err;
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err = rsmu_write_page_register(rsmu, reg);
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if (err)
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return err;
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err = rsmu_write_device(rsmu, addr, &data, 1);
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if (err)
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dev_err(rsmu->dev,
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"Failed to write offset address 0x%x\n", addr);
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return err;
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}
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static const struct regmap_config rsmu_cm_regmap_config = {
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.reg_bits = 32,
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.val_bits = 8,
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.max_register = 0x20120000,
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.reg_read = rsmu_reg_read,
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.reg_write = rsmu_reg_write,
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.cache_type = REGCACHE_NONE,
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};
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static const struct regmap_config rsmu_sabre_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x400,
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.reg_read = rsmu_reg_read,
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.reg_write = rsmu_reg_write,
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.cache_type = REGCACHE_NONE,
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};
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static int rsmu_spi_probe(struct spi_device *client)
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{
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const struct spi_device_id *id = spi_get_device_id(client);
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const struct regmap_config *cfg;
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struct rsmu_ddata *rsmu;
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int ret;
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rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL);
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if (!rsmu)
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return -ENOMEM;
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spi_set_drvdata(client, rsmu);
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rsmu->dev = &client->dev;
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rsmu->type = (enum rsmu_type)id->driver_data;
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/* Initialize regmap */
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switch (rsmu->type) {
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case RSMU_CM:
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cfg = &rsmu_cm_regmap_config;
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break;
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case RSMU_SABRE:
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cfg = &rsmu_sabre_regmap_config;
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break;
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default:
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dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type);
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return -ENODEV;
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}
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rsmu->regmap = devm_regmap_init(&client->dev, NULL, client, cfg);
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if (IS_ERR(rsmu->regmap)) {
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ret = PTR_ERR(rsmu->regmap);
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dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret);
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return ret;
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}
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return rsmu_core_init(rsmu);
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}
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static void rsmu_spi_remove(struct spi_device *client)
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{
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struct rsmu_ddata *rsmu = spi_get_drvdata(client);
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rsmu_core_exit(rsmu);
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}
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static const struct spi_device_id rsmu_spi_id[] = {
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{ "8a34000", RSMU_CM },
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{ "8a34001", RSMU_CM },
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{ "82p33810", RSMU_SABRE },
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{ "82p33811", RSMU_SABRE },
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{}
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};
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MODULE_DEVICE_TABLE(spi, rsmu_spi_id);
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static const struct of_device_id rsmu_spi_of_match[] = {
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{ .compatible = "idt,8a34000", .data = (void *)RSMU_CM },
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{ .compatible = "idt,8a34001", .data = (void *)RSMU_CM },
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{ .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE },
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{ .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE },
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{}
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};
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MODULE_DEVICE_TABLE(of, rsmu_spi_of_match);
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static struct spi_driver rsmu_spi_driver = {
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.driver = {
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.name = "rsmu-spi",
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.of_match_table = rsmu_spi_of_match,
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},
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.probe = rsmu_spi_probe,
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.remove = rsmu_spi_remove,
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.id_table = rsmu_spi_id,
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};
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static int __init rsmu_spi_init(void)
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{
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return spi_register_driver(&rsmu_spi_driver);
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}
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subsys_initcall(rsmu_spi_init);
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static void __exit rsmu_spi_exit(void)
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{
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spi_unregister_driver(&rsmu_spi_driver);
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}
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module_exit(rsmu_spi_exit);
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MODULE_DESCRIPTION("Renesas SMU SPI driver");
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MODULE_LICENSE("GPL");
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