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4c2241fd42
Implement arch specific irqsafe_cpu ops. The arch specific ops do not disable/enable interrupts since that is an expensive operation. Instead we disable preemption and perform a compare and swap loop. Since on server distros (the ones we care about) preemption is disabled the preempt_disable()/preempt_enable() pair is a nop. In the end this code should be faster than the generic one. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
225 lines
5.0 KiB
C
225 lines
5.0 KiB
C
/*
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* Copyright IBM Corp. 1999, 2011
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
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*/
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#ifndef __ASM_CMPXCHG_H
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#define __ASM_CMPXCHG_H
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#include <linux/types.h>
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, void *ptr, int size)
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{
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unsigned long addr, old;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" (x << shift), "d" (~(255 << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" (x << shift), "d" (~(65535 << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 4:
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asm volatile(
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" l %0,%3\n"
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"0: cs %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) ptr)
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: "d" (x), "Q" (*(int *) ptr)
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: "memory", "cc");
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return old;
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#ifdef CONFIG_64BIT
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case 8:
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asm volatile(
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" lg %0,%3\n"
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"0: csg %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(long *) ptr)
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: "d" (x), "Q" (*(long *) ptr)
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: "memory", "cc");
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return old;
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#endif /* CONFIG_64BIT */
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr, x) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__xchg((unsigned long)(x), (void *)(ptr), sizeof(*(ptr)));\
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__ret; \
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})
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long __cmpxchg(void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long addr, prev, tmp;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
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: "d" (old << shift), "d" (new << shift),
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"d" (~(255 << shift)), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
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: "d" (old << shift), "d" (new << shift),
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"d" (~(65535 << shift)), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev >> shift;
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case 4:
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asm volatile(
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" cs %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(int *) ptr)
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: "0" (old), "d" (new), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev;
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#ifdef CONFIG_64BIT
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case 8:
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asm volatile(
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" csg %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(long *) ptr)
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: "0" (old), "d" (new), "Q" (*(long *) ptr)
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: "memory", "cc");
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return prev;
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#endif /* CONFIG_64BIT */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#ifdef CONFIG_64BIT
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#define cmpxchg64(ptr, o, n) \
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({ \
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cmpxchg((ptr), (o), (n)); \
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})
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#else /* CONFIG_64BIT */
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static inline unsigned long long __cmpxchg64(void *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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register_pair rp_old = {.pair = old};
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register_pair rp_new = {.pair = new};
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asm volatile(
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" cds %0,%2,%1"
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: "+&d" (rp_old), "=Q" (ptr)
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: "d" (rp_new), "Q" (ptr)
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: "cc");
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return rp_old.pair;
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}
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#define cmpxchg64(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64((ptr), \
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(unsigned long long)(o), \
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(unsigned long long)(n)))
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#endif /* CONFIG_64BIT */
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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case 2:
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case 4:
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#ifdef CONFIG_64BIT
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case 8:
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#endif
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return __cmpxchg(ptr, old, new, size);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) cmpxchg64((ptr), (o), (n))
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#endif /* __ASM_CMPXCHG_H */
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