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The PWM controller on sun5i SoCs is identical to the one found on sun7i SoCs. On the A13 package only one of the 2 pins is routed to the outside, so only advertise one PWM channel there. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
23 lines
640 B
Plaintext
23 lines
640 B
Plaintext
Allwinner sun4i and sun7i SoC PWM controller
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Required properties:
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- compatible: should be one of:
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- "allwinner,sun4i-a10-pwm"
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- "allwinner,sun5i-a10s-pwm"
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- "allwinner,sun5i-a13-pwm"
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- "allwinner,sun7i-a20-pwm"
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- reg: physical base address and length of the controller's registers
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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the cells format.
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- clocks: From common clock binding, handle to the parent clock.
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Example:
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pwm: pwm@01c20e00 {
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compatible = "allwinner,sun7i-a20-pwm";
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reg = <0x01c20e00 0xc>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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