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9896c7b57e
We get support for three new 32-bit SoC platforms this time. The amount of changes in arch/arm for any of them is miniscule, as all the interesting code is in device driver subsystems (irqchip, clk, pinctrl, ...) these days. I'm listing them here, as the addition of the Kconfig statement is the main relevant milestone for a new platform. In each case, some drivers are are shared with existing platforms, while other drivers are added for v4.7 as well, or come in a later release. - The Aspeed platform is probably the most interesting one, this is what most whitebox servers use as their baseboard management controller. We get support for the very common ast2400 and ast2500 SoCs. The OpenBMC project focuses on this chip, and the LWN article about their ELC 2016 presentation at https://lwn.net/Articles/683320/ triggered the submission, but the code comes from IBM's OpenPOWER team rather than the team at Facebook. There are still a lot more drivers that need to get added over time, and I hope both teams can work together on that. - OXNAS is an old platform for Network Attached Storage devices from Oxford Semiconductor. There are models with ARM10 (!) and ARM11MPCore cores, but for now, we only support the original ARM9 based versions. The product lineup was subsequently part of PLX, Avago and now the new Broadcom Ltd. https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas has some more information. - V2M-MPS2 is a prototyping platform from ARM for their Cortex-M cores and is related to the existing Realview / Versatile Express lineup, but without MMU. We now support various NOMMU platforms, so adding a new one is fairly straightforward. http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/ has detailed information about the platform. Other noteworthy updates: - Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain Lemieux are now maintaining the platform. This is an older ARM9 based platform from NXP (not Freescale), but it remains in use in embedded markets. - Kevin Hilman is now co-maintaining the Amlogic Meson platform for both 32-bit and 64-bit ARM, and started contributing some patches. - As is often the case, work on the OMAP platforms makes up the bulk of the actual SoC code changes in arch/arm, but there isn't a lot of that either. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAVzuXX2CrR//JCVInAQLTghAA0f+2V2wC6HVBfDhT1YmhbAkPF1KzgLbB h30fN6BtIe9mE3kR69uWgwPSzn4hTKEQXoC9m6S+XClTn6MKPrbCEYDZl4ZwIER8 XDamxJV+6oTG+GKtKpHFkC4WPJkLthEuD34gr2xU8DFrU+y2Y5QNXi5wvSsBp8WS 6C/70HQEy35uSyOjbjVlPi0/UKoelVw9dCO7HZBOb9lTd88hC4Gx90KFwpq6Ievf L20VNgOESC2y6kRbuLNbhQVsbT2Ijyz9NccVM5owFEbHkXDxJ0vQVzrNM999DVjb CC2v0NZMLPNJQn2RvC172QBOsOERxIRkZdJHcifydl7i2QNpr8+/YSnS7OSx3dA/ 3ZmTLejaiGUXdTGEI9dHy77s+adwTzGsH+INKotQG8qwUXzCLuUWN3GGK+Qof5Rk jbsGAoZ7GQz1/7NdEOcGW6pxD4mllk3McKMzNlMmddRDUPhSUg3WXu0c1AWGzfA1 ulk6fQDaTUjvs7nokuozhguKz8OKrT6S7x/iES5tPbXLhuDqfnUdYiQ+7m2beRb5 L9S9KK95HXnKJAI9WLOELj1vCrfbCGjlwz8YVSrwPtwwzP/wbB1Ni6tmwLrxHbLk SGyJEMnPs3mARIPDwDysyOs+3OUSx04uYW6YTSh8XyKNIxTCflRxr/iM5YyYEMvt lXMrp1sh4hc= =5oFu -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "We get support for three new 32-bit SoC platforms this time. The amount of changes in arch/arm for any of them is miniscule, as all the interesting code is in device driver subsystems (irqchip, clk, pinctrl, ...) these days. I'm listing them here, as the addition of the Kconfig statement is the main relevant milestone for a new platform. In each case, some drivers are are shared with existing platforms, while other drivers are added for v4.7 as well, or come in a later release. - The Aspeed platform is probably the most interesting one, this is what most whitebox servers use as their baseboard management controller. We get support for the very common ast2400 and ast2500 SoCs. The OpenBMC project focuses on this chip, and the LWN article about their ELC 2016 presentation at https://lwn.net/Articles/683320/ triggered the submission, but the code comes from IBM's OpenPOWER team rather than the team at Facebook. There are still a lot more drivers that need to get added over time, and I hope both teams can work together on that. - OXNAS is an old platform for Network Attached Storage devices from Oxford Semiconductor. There are models with ARM10 (!) and ARM11MPCore cores, but for now, we only support the original ARM9 based versions. The product lineup was subsequently part of PLX, Avago and now the new Broadcom Ltd. https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas has some more information. - V2M-MPS2 is a prototyping platform from ARM for their Cortex-M cores and is related to the existing Realview / Versatile Express lineup, but without MMU. We now support various NOMMU platforms, so adding a new one is fairly straightforward. http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/ has detailed information about the platform. Other noteworthy updates: - Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain Lemieux are now maintaining the platform. This is an older ARM9 based platform from NXP (not Freescale), but it remains in use in embedded markets. - Kevin Hilman is now co-maintaining the Amlogic Meson platform for both 32-bit and 64-bit ARM, and started contributing some patches. - As is often the case, work on the OMAP platforms makes up the bulk of the actual SoC code changes in arch/arm, but there isn't a lot of that either" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) MAINTAINERS: ARM/Amlogic: add co-maintainer, misc. updates MAINTAINERS: add ARM/NXP LPC32XX SoC specific drivers to the section MAINTAINERS: add new maintainers of NXP LPC32xx SoC MAINTAINERS: move ARM/NXP LPC32xx record to ARM section arm: Add Aspeed machine ARM: lpc32xx: remove duplicate const on lpc32xx_auxdata_lookup ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers ARM: lpc32xx: remove reboot header file ARM: dove: Remove CLK_IS_ROOT ARM: orion5x: Remove CLK_IS_ROOT ARM: mv78xx0: Remove CLK_IS_ROOT ARM: davinci: da850: use clk->set_parent for async3 ARM: davinci: Move clock init after ioremap. MAINTAINERS: Update ARM Versatile Express platform entry ARM: vexpress/mps2: introduce MPS2 platform MAINTAINERS: add maintainer entry for ARM/OXNAS platform ARM: Add new mach-oxnas irqchip: versatile-fpga: add new compatible for OX810SE SoC ARM: uniphier: correct the call order of of_node_put() MAINTAINERS: fix stale TI DaVinci entries ...
124 lines
2.9 KiB
C
124 lines
2.9 KiB
C
/*
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* Code commons to all DaVinci SoCs.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2009 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/etherdevice.h>
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#include <linux/davinci_emac.h>
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#include <linux/dma-mapping.h>
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/cputype.h>
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#include "clock.h"
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struct davinci_soc_info davinci_soc_info;
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EXPORT_SYMBOL(davinci_soc_info);
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void __iomem *davinci_intc_base;
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int davinci_intc_type;
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void davinci_get_mac_addr(struct nvmem_device *nvmem, void *context)
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{
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char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
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off_t offset = (off_t)context;
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if (!IS_BUILTIN(CONFIG_NVMEM)) {
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pr_warn("Cannot read MAC addr from EEPROM without CONFIG_NVMEM\n");
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return;
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}
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/* Read MAC addr from EEPROM */
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if (nvmem_device_read(nvmem, offset, ETH_ALEN, mac_addr) == ETH_ALEN)
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pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
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}
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static int __init davinci_init_id(struct davinci_soc_info *soc_info)
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{
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int i;
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struct davinci_id *dip;
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u8 variant;
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u16 part_no;
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void __iomem *base;
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base = ioremap(soc_info->jtag_id_reg, SZ_4K);
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if (!base) {
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pr_err("Unable to map JTAG ID register\n");
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return -ENOMEM;
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}
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soc_info->jtag_id = __raw_readl(base);
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iounmap(base);
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variant = (soc_info->jtag_id & 0xf0000000) >> 28;
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part_no = (soc_info->jtag_id & 0x0ffff000) >> 12;
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for (i = 0, dip = soc_info->ids; i < soc_info->ids_num;
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i++, dip++)
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/* Don't care about the manufacturer right now */
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if ((dip->part_no == part_no) && (dip->variant == variant)) {
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soc_info->cpu_id = dip->cpu_id;
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pr_info("DaVinci %s variant 0x%x\n", dip->name,
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dip->variant);
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return 0;
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}
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pr_err("Unknown DaVinci JTAG ID 0x%x\n", soc_info->jtag_id);
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return -EINVAL;
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}
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void __init davinci_common_init(struct davinci_soc_info *soc_info)
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{
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int ret;
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if (!soc_info) {
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ret = -EINVAL;
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goto err;
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}
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memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info));
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if (davinci_soc_info.io_desc && (davinci_soc_info.io_desc_num > 0))
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iotable_init(davinci_soc_info.io_desc,
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davinci_soc_info.io_desc_num);
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/*
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* Normally devicemaps_init() would flush caches and tlb after
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* mdesc->map_io(), but we must also do it here because of the CPU
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* revision check below.
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*/
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local_flush_tlb_all();
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flush_cache_all();
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/*
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* We want to check CPU revision early for cpu_is_xxxx() macros.
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* IO space mapping must be initialized before we can do that.
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*/
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ret = davinci_init_id(&davinci_soc_info);
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if (ret < 0)
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goto err;
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return;
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err:
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panic("davinci_common_init: SoC Initialization failed\n");
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}
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void __init davinci_init_late(void)
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{
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davinci_cpufreq_init();
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davinci_pm_init();
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davinci_clk_disable_unused();
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}
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