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Some platforms, such as the DNS-323 rev C requires the soft reset line to be toggled on and back off for the reset to work. Note: The choice of 200ms delay comes from the 2.6.12 based vendor kernel. It seems to be a -lot- though and I had my device working fine with much smaller delays but better safe... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
34 lines
677 B
C
34 lines
677 B
C
/*
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* arch/arm/mach-orion5x/include/mach/system.h
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_SYSTEM_H
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#define __ASM_ARCH_SYSTEM_H
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#include <mach/bridge-regs.h>
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static inline void arch_idle(void)
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{
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cpu_do_idle();
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}
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static inline void arch_reset(char mode, const char *cmd)
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{
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/*
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* Enable and issue soft reset
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*/
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orion5x_setbits(RSTOUTn_MASK, (1 << 2));
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orion5x_setbits(CPU_SOFT_RESET, 1);
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mdelay(200);
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orion5x_clrbits(CPU_SOFT_RESET, 1);
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}
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#endif
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