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3ac40c404c
Clarify locking.rst to mention early that we're not enabling fast page fault for indirect sps. The previous wording is confusing, in that it seems the proposed solution has been already implemented but it has not. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
243 lines
11 KiB
ReStructuredText
243 lines
11 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=================
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KVM Lock Overview
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=================
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1. Acquisition Orders
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---------------------
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The acquisition orders for mutexes are as follows:
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- kvm->lock is taken outside vcpu->mutex
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- kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock
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- kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
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them together is quite rare.
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On x86, vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock.
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Everything else is a leaf: no other lock is taken inside the critical
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sections.
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2. Exception
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------------
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Fast page fault:
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Fast page fault is the fast path which fixes the guest page fault out of
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the mmu-lock on x86. Currently, the page fault can be fast in one of the
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following two cases:
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1. Access Tracking: The SPTE is not present, but it is marked for access
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tracking i.e. the SPTE_SPECIAL_MASK is set. That means we need to
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restore the saved R/X bits. This is described in more detail later below.
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2. Write-Protection: The SPTE is present and the fault is
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caused by write-protect. That means we just need to change the W bit of
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the spte.
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What we use to avoid all the race is the SPTE_HOST_WRITEABLE bit and
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SPTE_MMU_WRITEABLE bit on the spte:
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- SPTE_HOST_WRITEABLE means the gfn is writable on host.
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- SPTE_MMU_WRITEABLE means the gfn is writable on mmu. The bit is set when
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the gfn is writable on guest mmu and it is not write-protected by shadow
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page write-protection.
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On fast page fault path, we will use cmpxchg to atomically set the spte W
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bit if spte.SPTE_HOST_WRITEABLE = 1 and spte.SPTE_WRITE_PROTECT = 1, or
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restore the saved R/X bits if VMX_EPT_TRACK_ACCESS mask is set, or both. This
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is safe because whenever changing these bits can be detected by cmpxchg.
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But we need carefully check these cases:
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1) The mapping from gfn to pfn
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The mapping from gfn to pfn may be changed since we can only ensure the pfn
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is not changed during cmpxchg. This is a ABA problem, for example, below case
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will happen:
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+------------------------------------------------------------------------+
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| At the beginning:: |
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| |
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| gpte = gfn1 |
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| gfn1 is mapped to pfn1 on host |
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| spte is the shadow page table entry corresponding with gpte and |
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| spte = pfn1 |
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+------------------------------------------------------------------------+
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| On fast page fault path: |
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+------------------------------------+-----------------------------------+
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| CPU 0: | CPU 1: |
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+------------------------------------+-----------------------------------+
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| :: | |
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| | |
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| old_spte = *spte; | |
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+------------------------------------+-----------------------------------+
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| | pfn1 is swapped out:: |
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| | |
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| | spte = 0; |
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| | |
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| | pfn1 is re-alloced for gfn2. |
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| | |
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| | gpte is changed to point to |
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| | gfn2 by the guest:: |
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| | |
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| | spte = pfn1; |
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+------------------------------------+-----------------------------------+
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| :: |
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| if (cmpxchg(spte, old_spte, old_spte+W) |
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| mark_page_dirty(vcpu->kvm, gfn1) |
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| OOPS!!! |
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+------------------------------------------------------------------------+
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We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
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For direct sp, we can easily avoid it since the spte of direct sp is fixed
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to gfn. For indirect sp, we disabled fast page fault for simplicity.
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A solution for indirect sp could be to pin the gfn, for example via
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kvm_vcpu_gfn_to_pfn_atomic, before the cmpxchg. After the pinning:
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- We have held the refcount of pfn that means the pfn can not be freed and
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be reused for another gfn.
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- The pfn is writable and therefore it cannot be shared between different gfns
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by KSM.
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Then, we can ensure the dirty bitmaps is correctly set for a gfn.
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2) Dirty bit tracking
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In the origin code, the spte can be fast updated (non-atomically) if the
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spte is read-only and the Accessed bit has already been set since the
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Accessed bit and Dirty bit can not be lost.
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But it is not true after fast page fault since the spte can be marked
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writable between reading spte and updating spte. Like below case:
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+------------------------------------------------------------------------+
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| At the beginning:: |
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| |
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| spte.W = 0 |
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| spte.Accessed = 1 |
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+------------------------------------+-----------------------------------+
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| CPU 0: | CPU 1: |
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+------------------------------------+-----------------------------------+
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| In mmu_spte_clear_track_bits():: | |
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| old_spte = *spte; | |
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| /* 'if' condition is satisfied. */| |
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| if (old_spte.Accessed == 1 && | |
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| old_spte.W == 0) | |
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| spte = 0ull; | |
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+------------------------------------+-----------------------------------+
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| | on fast page fault path:: |
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| | |
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| | spte.W = 1 |
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| | memory write on the spte:: |
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| | spte.Dirty = 1 |
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+------------------------------------+-----------------------------------+
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| :: | |
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| else | |
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| old_spte = xchg(spte, 0ull) | |
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| if (old_spte.Accessed == 1) | |
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| kvm_set_pfn_accessed(spte.pfn);| |
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| if (old_spte.Dirty == 1) | |
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| kvm_set_pfn_dirty(spte.pfn); | |
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| OOPS!!! | |
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+------------------------------------+-----------------------------------+
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The Dirty bit is lost in this case.
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In order to avoid this kind of issue, we always treat the spte as "volatile"
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if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
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the spte is always atomically updated in this case.
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3) flush tlbs due to spte updated
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If the spte is updated from writable to readonly, we should flush all TLBs,
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otherwise rmap_write_protect will find a read-only spte, even though the
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writable spte might be cached on a CPU's TLB.
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As mentioned before, the spte can be updated to writable out of mmu-lock on
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fast page fault path, in order to easily audit the path, we see if TLBs need
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be flushed caused by this reason in mmu_spte_update() since this is a common
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function to update spte (present -> present).
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Since the spte is "volatile" if it can be updated out of mmu-lock, we always
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atomically update the spte, the race caused by fast page fault can be avoided,
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See the comments in spte_has_volatile_bits() and mmu_spte_update().
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Lockless Access Tracking:
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This is used for Intel CPUs that are using EPT but do not support the EPT A/D
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bits. In this case, when the KVM MMU notifier is called to track accesses to a
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page (via kvm_mmu_notifier_clear_flush_young), it marks the PTE as not-present
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by clearing the RWX bits in the PTE and storing the original R & X bits in
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some unused/ignored bits. In addition, the SPTE_SPECIAL_MASK is also set on the
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PTE (using the ignored bit 62). When the VM tries to access the page later on,
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a fault is generated and the fast page fault mechanism described above is used
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to atomically restore the PTE to a Present state. The W bit is not saved when
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the PTE is marked for access tracking and during restoration to the Present
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state, the W bit is set depending on whether or not it was a write access. If
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it wasn't, then the W bit will remain clear until a write access happens, at
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which time it will be set using the Dirty tracking mechanism described above.
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3. Reference
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------------
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:Name: kvm_lock
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:Type: mutex
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:Arch: any
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:Protects: - vm_list
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:Name: kvm_count_lock
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:Type: raw_spinlock_t
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:Arch: any
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:Protects: - hardware virtualization enable/disable
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:Comment: 'raw' because hardware enabling/disabling must be atomic /wrt
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migration.
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:Name: kvm_arch::tsc_write_lock
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:Type: raw_spinlock
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:Arch: x86
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:Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
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- tsc offset in vmcb
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:Comment: 'raw' because updating the tsc offsets must not be preempted.
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:Name: kvm->mmu_lock
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:Type: spinlock_t
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:Arch: any
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:Protects: -shadow page/shadow tlb entry
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:Comment: it is a spinlock since it is used in mmu notifier.
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:Name: kvm->srcu
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:Type: srcu lock
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:Arch: any
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:Protects: - kvm->memslots
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- kvm->buses
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:Comment: The srcu read lock must be held while accessing memslots (e.g.
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when using gfn_to_* functions) and while accessing in-kernel
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MMIO/PIO address->device structure mapping (kvm->buses).
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The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu
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if it is needed by multiple functions.
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:Name: blocked_vcpu_on_cpu_lock
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:Type: spinlock_t
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:Arch: x86
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:Protects: blocked_vcpu_on_cpu
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:Comment: This is a per-CPU lock and it is used for VT-d posted-interrupts.
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When VT-d posted-interrupts is supported and the VM has assigned
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devices, we put the blocked vCPU on the list blocked_vcpu_on_cpu
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protected by blocked_vcpu_on_cpu_lock, when VT-d hardware issues
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wakeup notification event since external interrupts from the
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assigned devices happens, we will find the vCPU on the list to
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wakeup.
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