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The Allwinner A31 SoC using that IP has a reset controller maintaining it reset unless told otherwise. Add some optional reset support to the driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
38 lines
1.1 KiB
Plaintext
38 lines
1.1 KiB
Plaintext
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* Marvell MV64XXX I2C controller
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Required properties :
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- reg : Offset and length of the register set for the device
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- compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
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or "marvell,mv78230-i2c" or "marvell,mv78230-a0-i2c"
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Note: Only use "marvell,mv78230-a0-i2c" for a very rare,
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initial version of the SoC which had broken offload
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support. Linux auto-detects this and sets it
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appropriately.
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- interrupts : The interrupt number
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Optional properties :
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- clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
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default frequency is 100kHz
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- resets : phandle to the parent reset controller
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Examples:
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i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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interrupts = <29>;
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clock-frequency = <100000>;
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};
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For the Armada XP:
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i2c@11000 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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interrupts = <29>;
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clock-frequency = <100000>;
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};
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